International Business Machines Corporation

Massimo V Fischetti

Paul Michael Solomon

Alexander Reznicek

Min Yang

Chun-Yung Sung

Victor Chan

Rajesh Rengarajan

John Michael Hergenrother

Meikei Ieong

Qiqing Christine Ouyang

Hon-Sum Philip Wong

MeiKei Leong

Steven E Laux

A semiconductor (e.g., complementary metal oxide semiconductor (CMOS)) structure formed on a (110) substrate that has improved performance, in terms of mobility enhancement is provided. In accordance with the present invention, the inventive structure includes at least one of a single tensile stressed liner, a compressively stressed shallow trench isolation (STI) region, or a tensile stressed embedded well, which is used in conjunction with the (110) substrate to improve carrier mobility of both nFETs and pFETs. The present invention also relates to a method of providing such structures.

Higher performance CMOS on (110) wafers

The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a &#x3c;110&#x3e; crystal orientation and a biaxial compressive strain. The term 'biaxial compressive stress' is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing &#x3c;110&#x3e; layer; and creating a biaxial strain in the silicon-containing &#x3c;110&#x3e; layer.

Enhancement of electron and hole mobilities in &#x3c;110&#x3e; Si under biaxial compressive strain

A method (and structure) for an electronic chip having at least one layer of material for which a carrier mobility of a first carrier type is higher in a first crystal surface than in a second crystal surface and for which a carrier mobility of a second carrier type is higher in the second crystal surface than the first crystal surface includes a first device having at least one component fabricated on the first crystal surface of the material, wherein an activity of the component of the first device involves primarily the first carrier type, and a second device having at least one component fabricated on the second crystal surface of the material, wherein an activity of the component of the second device involves primarily the second carrier type.

Germanium field effect transistor and method of fabricating the same

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Putnam Valley, NY, United States of America

Massimo V Fischetti