Stmicroelectronics Gmbh

Stmicroelectronics S.r.l.

Massimo Scipioni

Riccardo Maggi

Carlo Alberto Romani

Corrado Giorgio Castiglione

Donato Tancredi

Elvio Romanucci

Stefano Cavallucci

A semiconductor device wherein a delay chain is integrated; the semiconductor device having a semiconductor layer. The delay chain includes a plurality of delay cells placed in the semiconductor layer and electrically connected to each other so as to form the delay chain. The semiconductor device includes a first and second metal lines respectively connected to a supply voltage and a reference voltage and placed in a longitudinal direction on a surface of the semiconductor layer; each delay cell of the plurality of cells is electrically connected with the first and second metal lines. Any delay cell and its successive or preceding delay cells of the delay chain are placed in a transversal direction with respect to the first or the second metal line.

Semiconductor device with integrated delay chain

An integrated circuit burn-in test system includes an integrated circuit and a tester. The integrated circuit includes operating circuitry, a heater for heating the operating circuitry, and burn-in test circuitry for testing the operating circuitry while being heated. A package surrounds the operating circuitry, the heater and the burn-in test circuitry. The burn-in test circuitry causes the operating circuitry to operate and generate data related thereto. The tester receives data from the burn-in test circuitry. The heater may be configured within the package to heat at least one predetermined portion of the operating circuitry.

Integrated circuit burn-in test system and associated methods

A system tests an integrated circuit at operational speed. The system includes a high frequency clock converter that receives test clock signals at a speed lower than operational speed of the integrated circuit to be tested. The high frequency clock converter generates test clock signals for operational speed testing of the integrated circuit.

System and method for testing integrated circuits at operational speed using high-frequency clock converter

The use of a PLL including a phase detector responsive to the phase difference between an input signal and a feedback signal and which pilots an oscillator in function of this difference, is envisaged. The PLL also includes a feedback path that is responsive to the signal generated by the oscillator and which generates said feedback signal via at least one divider with a variable division ratio. The division ratio of said divider is modulated via a sigma-delta modulator, the input of which is fed with a triangular-wave modulating signal. The preferred application is that of a spread spectrum clock generator (SSCG) for digital electronic systems.

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Portland, OR, United States of America

Massimo Scipioni