Agence Spatiale Europeenne

Stmicroelectronics S.r.l.

Consorzio Pisa Ricerche

Massimo Rovini

Luca Fanucci

Paolo Burzigotti

Francesco Rossi

Giovanni Vanini

Giuseppe Gentile

Alfonso Martinez

A configurable Turbo-LDPC decoder having A set of P&#x3e;1 Soft-Input-Soft-Output decoding units (DP-DP; DP) for iteratively decoding both Turbo- and LDPC-encoded input data, each of the decoding units having first (I) and second (I) input ports and first (O) and second (O) output ports for intermediate data; First and second memories (M, M) for storing the intermediate data, each of the first and second memories comprising P independently readable and writable memory blocks having respective input and output ports; and A configurable switching network (SN) for connecting the first input and output ports of the decoding units to the output and input ports of the first memory, and the second input and output ports of the decoding units to the output and input ports of the second memory.

Flexible channel decoder

An embodiment of a decoder for decoding a Low-Density Parity-Check encoded input data includes a serial processing unit operating in clock cycles to perform serial update of the layers in the code. Operations of the serial processing unit to produce output data for a current layer are pipelined with acquisition of input data for a next layer, whereby the current layer and the next layer may attempt to use soft output information common to both layers. The serial processing unit is configured for delaying acquisition of input data for the next layer over a number of idle clock cycles. Latency due to the idle clock cycles is minimized by selectively modifying the sequence of layers through the decoding process and the sequence of messages processed by a certain layer.

Methods and architectures for layered decoding of LDPC codes with minimum latency

An improved transmission method for high-rate digital communication on unshielded twisted copper pairs for Very-High Speed Digital Subscriber Loop (VDSL) modems. The new modulation scheme is a Multi Code Multi Carrier Code Division Multiple Access, hereafter named MCCDMA. The system takes advantage from both the CDMA modulation and the Multi-Carrier transmission and, in addition, the channel throughput is increased adopting a multi-code approach. The novel scheme encompasses transmitter, channel and receiver loading.

VDSL transmission employing multi-code multi carrier CDMA modulation

Iterative decoder comprising a plurality of servers which perform the iterative decoding of a data block each, an input buffer memory and a control unit which performs a statistical multiplexing of the data at input, which are firstly stored in the input buffer memory and successively processed by one of the servers. The input buffer memory comprises N+L memory locations, where N is the number of servers and L is the number of so-called additional locations. Each block to be decoded which is received while all the servers are busy is stored in one of the L additional locations possibly available, or it is lost if the input buffer memory is entirely filled. The number L of additional locations and the number N of servers are such that the probability Pof a block being lost, calculated on the basis of a queuing model of D/G/N/N+L type, satisfies the condition P&#x2266;&#x3b1;&#xb7;FER*, where FER* is the error rate in the blocks allowed and &#x3b1;&#x3c;1; typically &#x3b1; is of the order of 0.01. Process for manufacturing such an iterative decoder comprising a step of design and a step of hardware embodiment.

Growing community of inventors

Pisa, Italy

Massimo Rovini