Stmicroelectronics S.r.l.

Micron Technology Incorporated

Sgs-thomson Microelectronics S.r.l.

Massimo Montanaro

Paolo Rolandi

Marco Giovanni Fontana

Giorgio Oddone

Mauro Pagliato

Antonio Barcella

Anthony R Cabrera

Gerald A Kreifels

Fabio Enrico Carlo Disegni

Federico Goller

Carmelo Paolino

Marco Riva

Michele Febbrarino

Dario Falanga

A non-volatile memory receives a data read request from a processing core of a plurality of processing cores. The read request is directed to a data partition of a non-volatile memory. The non-volatile memory determines whether to process the read request using read-while-write collision management. When it is determined to process the read request using read-while-write collision management, an address associated with the read request is stored in an address register of a set of registers associated with the processing core. Write operations directed to the data partition are suspended. A read operation associated with the read request is executed while the write operations are suspended and data responsive to the read operation is stored in one or more data registers of the set of registers. The data stored in the one or more data registers of the set of registers is provided to the processing core.

Data memory access collision manager, device and method

Systems and methods for intra-sector re-ordered wear leveling include: detecting, in a memory device, a high wear sub-sector having a high wear level, the sub-sector residing in a first sector; determining a second sector of the memory device having a low wear level; swapping the first sector with the second sector; and re-ordering a position of at least one sub-sector of the first sector, the second sector, or both.

Memory wear leveling

Methods of wear leveling in a memory, and memories configured to perform such methods, are useful in extending cycling endurance in memories. Such methods include transferring data from a first block of the memory to a second block of the memory, erasing the first block, transferring data from a third block of the memory to the first block, erasing the third block, transferring data from the second block to the third block, swapping logical addresses for the first block and the third block with each other, and erasing the second block. Transferring data from the third block to the first block excludes a sub-sector of the third block that is to be erased.

Sub-sector wear leveling in memories

Methods and memories for wear leveling by sub-sectors of a block are provided. In one such method, data are transferred from a first block of the memory to a second block of the memory, excluding a sub-sector of the first block that is to be erased, logical addresses for the first block and the second block are swapped with each other, the first block is erased, data are transferred from a third block to the first block, logical addresses for the first block and the third block are swapped with each other, and the third block is erased.

A sense amplifier is provided that includes a measure branch receiving an input current to be detected, a reference branch receiving a reference current, and an equalizing circuit including a comparator. The equalizing circuit selectively equalizes a measure node of the measure branch with a reference node of the reference branch, and the comparator compares a voltage at the measure node of the measure branch with a voltage at the reference node of the reference branch. The equalizing circuit is such that, when activated, equalization of the measure node with the reference node is virtual and substantially does not involve a flow of current between the measure node and the reference node of the reference branch. The sense amplifier is particularly suited for reading memory cells of a semiconductor memory. Also provided is a method for sensing an input current.

Sense amplifier with equalizer

A parallel sense amplifier includes a measuring branch for receiving an input current to be measured, a plurality of reference branches each one for receiving a reference current, and a plurality of comparators each one for comparing a voltage at a measuring node along the measuring branch with a voltage at a reference node along a corresponding reference branch; the amplifier further includes a multiple current mirror for mirroring the input current into each reference branch.

Parallel sense amplifier with mirroring of the current to be measured into each reference branch

Described herein is an asynchronous serial dichotomic sense amplifier comprising a first comparator stage having a first input receiving the cell current flowing in the multilevel memory cell, the content of which is to be read, a second input receiving a first reference current, and an output supplying the first of the bits stored in the multilevel memory cell; a multiplexer stage having a selection input connected to the output of the first comparator stage, a first signal input receiving a second reference current, a second signal input receiving a third reference current, and a signal output selectively connectable to the first or the second signal input depending on the logic level present on the selection input; and a second comparator stage having a first input receiving the cell current, a second input connected to the signal output of the multiplexer stage, and an output supplying the second of the bits stored in the multilevel memory cell.

Reading circuit and method for a multilevel non-volatile memory

A charge pump having a phase-generator circuit generating phase signals and an oscillator circuit supplying a clock signal, a current-limitation circuit to limit the current flowing in the oscillator circuit, and a control circuit supplying on an output a control signal supplied to the current-limitation circuit. The control circuit has a first current mirror connected to a ground line, a second current mirror connected to a supply line, a cascode structure arranged between the first and the second current mirrors and connected to the output of the control circuit to compensate the effects on the control signal caused by sharp relative variations between the potential of the supply line and the potential of the ground line, and a compensation circuit to compensate the effects on the control signal caused by sharp relative variations between the potential of the supply line and the potential of the ground line and by slow variations in temperature.

Low-consumption charge pump for a nonvolatile memory

A circuit structure for reading data contained in an electrically programmable/erasable integrated non-volatile memory device includes a matrix of memory cells and at least one reference cell for comparison with a memory cell during a reading phase. The reference cell is incorporated in a reference cells sub-matrix which is structurally independent of the matrix of memory cells. Also provided is a conduction path between the matrix and the sub-matrix, which path includes bit lines of the sub-matrix of reference cells extended continuously into the matrix of memory cells.

Circuital structure for reading data in a non-volatile memory device

A circuit and method for programming a multilevel nonvolatile memory are disclosed. The circuit uses one or more address pins as one or more synchronization signals during a programming operation. The circuit includes a counter, controlled by the one or more address pins, for selecting a programming voltage to apply to an addressed memory cell. The circuit further includes compare circuitry for comparing the data value stored in the addressed memory cell with a desired data value. The counter is selectively incremented to apply a higher voltage for further programming of the addressed memory cell, based up the comparison.

Method and circuit for programming a multilevel non-volatile memory

A circuit structure for programming data in reference cells of an electrically programmable/erasable integrated non-volatile memory device includes a matrix of multi-level memory cells and a corresponding reference cell provided for comparison with a respective memory cell during the read phase. The reference cell is incorporated, along with other cells of the same type, in a reference cell sub-matrix which is structurally independent of the memory cell matrix and directly accessed from outside in the DMA mode. The bit lines of the sub-matrix branch off to a series of switches which are individually operated by respective control signals REF(i) issued from a logic circuit with the purpose of selectively connecting the bit lines to a single external I/O terminal through a single addressing line of the access DMA mode.

Circuital structure for programming data in a non-volatile memory device

The integrated device comprises a PMOS transistor and a voltage selector having an output connected to the bulk terminal of the PMOS transistor. The voltage selector comprises an input stage supplying a supply voltage or a programming voltage according to whether the device is in a reading step or in a programming step; a comparator connected to the output of the input stage, receiving a boosted voltage, and generating a first control signal, the state whereof depends upon the comparison of the voltages at the inputs of the comparator; a logic circuit connected to the output of the comparator and generating a second control signal, the state whereof depends upon the state of the first control signal and of a third-level signal; and a switching circuit controlled by the first control signal, by the second control signal, and by the third-level signal and supplying each time the highest among the supply voltage, the boosted voltage, and the programming voltage.

Integrated device with voltage selector

A voltage boosting device for speeding power-up of multilevel nonvolatile memories, including a voltage regulator and a charge pump and having an output terminal; the voltage regulator having a regulation terminal connected to the output terminal, and an output supplying a control voltage; the read charge pump having an output connected to the output terminal and supplying a read voltage. The device further includes an enable circuit connected to the output and having a pump enable output connected to a charge pump enable terminal and supplying a pump enable signal. The pump enable signal is set at a first logic level so as to activate the charge pump when the read voltage is lower than a nominal value. In addition, the device generates a power-up sync signal which activates a read operation when the read voltage reaches its nominal value and a chip enable signal is set at an active value.

Voltage boosting device, in particular for speeding power-up of multilevel nonvolatile memories

A method for testing memory cells, and in particular virgin memory cells, in a multilevel memory device having a plurality of memory cells. The method includes reading the individual memory cells that constitute a memory device and comparing each one of these memory cells with at least one reference memory cell at a time, so as to determine whether the threshold of the memory cells is lower than the threshold of the at least one reference memory cell or not; determining the number of the memory cells whose threshold is higher than the threshold of the at least one reference cell; the at least one reference memory cell being chosen with a gradually higher threshold; when the number of memory cells whose threshold is higher than a given reference threshold is found to be sufficiently lower than the number of redundancy memory cells provided in the memory device, assuming the given reference threshold as lower reference threshold for the memory device, determining a statistical distribution of the thresholds of the memory cells.

Method and circuit for testing memory cells in a multilevel memory device

The method comprises the steps of detecting the trailing edge of an initialization signal, and generating a read bias signal and a read activation signal for the cell, when the trailing edge of the initialization signal is detected. The signals of read bias and read activation have a ramp-like leading edge and both signals are disabled when reading of the cell is completed. Thereby, phenomena of soft-writing of the cell are avoided, and risks of erroneous readings are reduced.

Growing community of inventors

Pavia, Italy

Massimo Montanaro