Stmicroelectronics S.r.l.

Atmel Corporation

Stmicroelectronics Design and Application S.r.o.

Massimo Mazzucco

Gian Marco Bo

Paolo Pulici

Matthieu Thomas

Michele Suraci

A DC-DC converter circuit including at least: a first step down converter having a first pair of switching devices in a half bridge configuration. A second step down converter includes a second pair of switching devices in a half bridge configuration. The first and second step down converters are connected in parallel to an output node connected to an output coil and receive command signals. A feedback loop includes a synchronization module receiving the gate control signals of high side switching devices and adjusts as a function of the gate control signals a delay in a signal path from the command signal to each gate control signal of the high side switching device to synchronize the gate control signals.

DC-DC converter circuit with synchronization module and corresponding conversion method

A method manages hysteretic DC-DC buck converters each including a hysteretic comparator operating according to a respective hysteresis window. The method includes, in a given converter, verifying if a respective feedback voltage reaches a lower threshold in order to enter a switch-on period of the converter, The method comprises: while the verifying indicates that the lower threshold is not reached, detecting if another converter has entered a respective switch on period and, in the affirmative, entering a hysteresis voltage adjustment procedure, include increasing by a given amount the amplitude of the hysteresis window of the given converter by reducing the lower threshold of the hysteresis window.

Method for managing a plurality of hysteretic DC-DC buck converters and corresponding DC-DC buck converter

A circuit for limiting a power current from a power-controlling pass device, the power-controlling pass device being coupled to a supply voltage, comprises the following. A sense device is coupled to the supply voltage with the sense device being configured to draw a sense current that is proportional to the power current. A current mirror is coupled to the sense device and the supply voltage through a low impedance node, the current mirror being configured to draw a mirror current through the low impedance node that is relative to the sense current. A limiting device is coupled to the supply voltage, the power-controlling pass device, and the low impedance node, the limiting device being configured to limit the power current according to a voltage difference between the low impedance node and the supply voltage.

Method and apparatus for current limitation in voltage regulators

A circuit for limiting a power current from a power-controlling pass device, the power-controlling pass device being coupled to a supply voltage, comprises the following. A sense device is coupled to the supply voltage with the sense device being configured to draw a sense current that is proportional to the power current. A current mirror is coupled to the sense device and the supply voltage through a low impedance node, the current mirror being configured to draw a mirror current through the low impedance node that is relative to the sense current. A limiting device is coupled to the supply voltage, the power-controlling pass device, and the low impedance node, the limiting device being configured to limit the power current according to a voltage difference between the low impedance node and the supply voltage. A resistance device or PMOS transistor that generates the voltage difference and that may be controlled through a proper bias circuit to adjust the voltage difference.

Growing community of inventors

Savona, Italy

Massimo Mazzucco