Micron Technology Incorporated

Other

Lodestar Licensing Group LLC

Massimo Iaculo

Giuseppe D'Eliseo

Paolo Papa

Carminantonio Manganelli

Alberto Sassara

Luigi Esposito

Francesco Falanga

Eric Kwok Fung Yuen

Antonino Pollio

Angelo Della Monica

Xinghui Duan

Ornella Vitale

Giuseppe Ferrari

Lalla Fatima Drissi

Danilo Caraccio

Francesco Basso

Giovanni Campardo

Federico Tiziani

Claudio Giaccio

Manuela Scognamiglio

Crescenzo Attanasio

Pasquale Cimmino

Yoav Weinberg

Lucia Santojanni

Salvatore Del Prete

Cimmino Pasquale

Falanga Francesco

Minopoli Dionisio

Marco Ferrara

Campardo Giovanni

Basso Francesco

Erika Morvillo

Gerard J Perdaems

Emanuele Confalonieri

Luca Porzio

Nadav Grosz

Roberto Izzi

Stefano Zanardi

Domenico Monteleone

Giovanni Guerra

Nicola Guida

Andrea Ruggiero

Nicola Cavaliere

Antonio Eliso

Methods, systems, and devices for idle mode temperature control for memory systems are described. A memory system may implement the use of one or more dummy access commands to reduce the effects of errors introduced by temperature changes while the memory system is in an idle mode. For example, performing one or more access commands, such as one or more read commands, may increase a temperature of a memory device and support a desired operating temperature for the memory device while the memory system is in the idle mode. The memory system may measure the temperature of the memory device during the idle mode. If the memory system determines that the temperature of the memory device has fallen below a threshold temperature, the memory system may issue a quantity of dummy access commands to the memory device, and the corresponding dummy access operations may result in a temperature increase at the memory device.

Idle mode temperature control for memory systems

Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.

Clustered parity for NAND data placement schema

Methods, systems, and devices for read disturb management for memory are described. In some instances, data may be read from a first page of a virtual block of a memory system. If the data includes one or more errors, the memory system may read data from a second page of the virtual block and determine whether one or more errors exist in the data. The memory system may continue reading pages of the virtual block until a page includes no (or relatively few errors). The memory system may then refresh the pages.

Read disturb management for memory

Methods, systems, and devices for data relocation operation techniques are described. A memory system may include blocks of memory cells, for example, within a non-volatile memory device of the memory system. The memory system may identify a command to perform a data relocation operation associated with a block of memory cells and may select between a first procedure and a second procedure for performing the data relocation operation. The memory system may select between the first procedure and the second procedure based on whether one or more parameters associated with the data relocation operation satisfy a threshold. For example, the memory system may select the first procedure if the one or more parameters satisfy the threshold and may select the second procedure if the one or more parameters do not satisfy the threshold. The memory system may perform the data relocation operation using the selected procedure.

Data relocation operation techniques

NAND data placement schema

Methods, systems, and devices for device fault condition reporting are described. A host system may transmit, to a memory system, a command to perform an operation. The memory system may receive the command and identify a fault condition associated with performing the operation. The memory system may transmit, to the host system, a message that indicates the fault condition. After the memory system transmits the message, the memory system may enter a safe mode of operation based on identifying the fault condition.

Device fault condition reporting

Devices and techniques for corrupted storage portion recovery in a memory device are described herein. A failure event can be detected during a garbage collection operation on a collection of storage portions (e.g., pages) in a memory array. Here, members of the collection of storage portions are being moved from a former physical location to a new physical location by the garbage collection operation. A reference to a former physical location of a possibly corrupt storage portion in the collection of storage portions can be retrieved in response to the failure event. Here, the possibly corrupt storage portion has already been written to a new physical location as part of the garbage collection operation. The possibly corrupt storage portion can then be rewritten at the new physical location using data from the former physical location.

Corrupted storage portion recovery in a memory device

A variety of applications can include systems and methods that control a memory size of a changelog in a storage device, where the changelog is implemented to correlate virtual page addresses to physical addresses in one or more memory devices. The memory size can be controlled by an allocation schema for a scalable memory area for the changelog in the storage device. The allocation schema can include using bitmaps, lists linked to the bitmaps, and a counter to count bits asserted in the bitmaps such that the allocation of memory space in the storage device can depend on usage rather than allocating a large memory space for all possible correlations of virtual page addresses to physical addresses.

Allocation schema for a scalable memory area

In various embodiments, techniques can be provided to address debug efficiency for failures found on an operational system. The techniques can utilize a real-time trigger to notify a memory device to dump an error log to timely capture all needed information. In response to detecting one or more error conditions associated with the memory device, a system that interfaces with the memory device can generate a trigger signal to the memory device. In response to identifying the trigger signal, the memory device can dump an error log of the memory device to a memory component in the memory device. The error log can later be retrieved from the memory component for failure analysis.

Real-time trigger to dump an error log

Methods, systems, and devices for data caching for fast system boot-up are described. A memory system may create a linked mapping of addresses, which may also be referred to as a mixed page pointer table. The linked mapping may include logical addresses associated with commands received during a boot-up procedure, and their associated physical addresses. The linked mapping may also include a counter associated with each logical address to track how often the logical address is referenced during successive boot-up procedures. Over successive boot-up procedures, addresses may be added or removed from the linked mapping, and sequential addresses may be compressed. The memory device may use the linked mapping to predict which data may be accessed during the boot-up procedure, and may pre-transfer the data to volatile memory based on the prediction.

Data caching for fast system boot-up

Devices and techniques for NAND logical-to-physical table region tracking are described herein. A write request, including a logical page and data to be written at the logical page, is received at a controller of a NAND device. The NAND controller may then establish an entry in a logical-to-physical (L2P) mapping table between the logical page and a physical page of a physical block of the NAND device to which the data is written. Here, the entry may be in a region of the L2P mapping table that is one of multiple regions. An indication of the region may be written in a data structure corresponding to the physical block.

NAND logical-to-physical table region tracking

Methods, systems, and devices for data defragmentation for a system boot procedure are described. The memory system may determine a write random index associated with a boot procedure. The write random index may indicate a relationship between a first quantity of sequential logical addresses accessed as part of the boot procedure and a second quantity of random logical addresses accessed as part of the boot procedure. The memory system may determine whether the write random index satisfies a threshold based on determining the write random index. In some cases, the memory system may transfer, to a second portion of the memory system, data stored in a first portion of the memory system based on determining that the write random index satisfies the threshold. The memory system may receive a request to perform the boot procedure after transferring the data and output, to the host system, the data transferred.

Data defragmentation for a system boot procedure having random indexes indicating a relationship between sequential logical addresses and random logical addresses

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San Marco Evangelista, Italy

Massimo Iaculo