Micron Technology Incorporated

Massimo Ernesto Bertuccio

Angelo Visconti

Mattia Robustelli

Augusto Benvenuti

Daniele Cantarelli

Laura Tatiana Czeppel

Silvia Beltrami

Sead Zildzic, Jr

Slivia Beltrami

A memory device includes an array of memory cells, a plurality of access lines, and a controller. The array of memory cells includes a plurality of strings of series-connected memory cells. The controller is configured to access the array of memory cells to program a selected memory cell of the array of memory cells to a first target level. The controller is further configured to apply a first voltage level to a first access line connected to the selected memory cell, and-apply a second voltage level higher than the first voltage level to a second access line adjacent to the first access line, apply a third voltage level between the first voltage level and the second voltage level to a third access line adjacent to the first access line and connected to an erased memory cell, and sense a first threshold voltage of the selected memory cell.

Memory devices with a lower effective program verify level

Apparatus might include an array of memory cells comprising a plurality of strings of series-connected memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to perform a sense operation on a selected memory cell of a string of series-connected memory cells, and to discharge access lines connected to the string of series-connected memory cells in a defined manner following the sense operation.

Apparatus for mitigating program disturb

Memories might include an array of memory cells comprising a plurality of strings of series-connected memory cells and a controller for access of the array of memory cells, wherein the controller is configured to perform a sense operation on a particular memory cell of a string of series-connected memory cells, discharge the access line for a second memory cell of the string of series-connected memory cells to a first voltage level and discharge the access line for the particular memory cell to a second voltage level higher than the first voltage level after completion of the sense operation, and discharge the access line for a third memory cell of the string of series-connected memory cells to a third voltage level lower than the second voltage level and higher than the first voltage level after initiating the discharge of the access line for the particular memory cell.

Memories for mitigating program disturb

Methods of operating a memory, and memory configured to perform similar methods, might include performing a sense operation on a particular memory cell of a string of series-connected memory cells, discharging the respective access line for a second memory cell of the string of series-connected memory cells to a first voltage level, discharging the respective access line for the particular memory cell to a second voltage level higher than the first voltage level, and discharging the respective access line for a third memory cell of the string of series-connected memory cells to a third voltage level lower than the second voltage level and higher than the first voltage level.

Apparatus and methods for mitigating program disturb

Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a memory device.

Growing community of inventors

San Donato Milanese, Italy

Massimo Ernesto Bertuccio