Nxp B.v.

Nxp Usa, Inc.

Massimo Ciacci

Ghiath Al-kadi

Remco Cornelis Herman Van De Beek

Remco Van De Beek

Jos Verlinden

Ghiath Al-Kadi

Lucien Johannes Breems

Juhui Li

Jan Hoogerbrugge

Alessio Filippi

Arie Geert Cornelis Koppelaar

Johannes Hubertus Antonius Brekelmans

Marco Berkhout

Muhammed Bolatkale

Robert Rutten

Martin Kessel

Shagun Bajoria

Fred Mostert

Manfred Zupke

Mattheus Johan Koerts

Soheil Bahrami

Ghaith Al-kadi

Remco C VandeBeek

Adaickalavan Meiyappan

Jos Verlinde

Remco CH Van De Beek

Interference cancellation is provided, according to certain aspects, by a filter, a signal detection circuit, synthesis circuitry and signal-generation circuitry. The filter is used to filter an incoming signal having an associated signal-to-noise metric and to output therefrom a filtered signal having an interference attribute of the incoming signal by amplification and/or isolation. The signal detection circuit is used to detect the interference attribute in the filtered signal. The synthesis circuitry is used to synthesize interference in the incoming signal based on the interference attribute. The signal-generation circuitry is used to generate, in response to the synthesized interference in the incoming signal, a filtered version of the incoming signal which provides an improved signal-to-noise metric.

Systems and methods involving interference cancellation

Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal.

Signal processing and conversion

Aspects are directed to an amplifier circuit including a signal processing circuit and a calibration circuit. In certain specific embodiments, the signal processing circuit includes a signal combiner and a closed-loop feedback path, and the signal processing circuit is designed to provide a loop transfer function for a derived signal partly representing contributions from an audio input signal, a control or pilot signal having a target frequency range, and a calibration signal. The signal combiner is designed to combine aspects of the control or pilot signal and aspects of the audio input signal, and the calibration circuit is designed to adjust an effective gain of the derived signal in response to whether a unity-gain frequency of a signal in the closed-loop feedback path, as provided via the loop transfer function, is higher or lower than the target frequency range. Consistent therewith and in yet more specific embodiments, such an amplifier circuit can define the target frequency range relative to the transfer function and an associated unity-gain frequency.

Automatic loop gain calibration in amplification circuits

A differential detector for a receiver and a method of detecting the value of symbols of a signal is disclosed. In particular, a detector comprising: an analog to digital converter for sampling samples from symbols of a signal; a differentiator configured to differentiate the samples with a transfer function to produce a differentiated series of samples for each symbol; and a decision device configured to determine the value of each symbol by comparing values of the differentiated series of samples with boundary condition values.

Detector

A system and module for, and a method of correcting, memory misalignment in a phase shift keying receiver is disclosed. Embodiments include a system having: an analog front end for receiving a demodulated signal having a preamble portion, and for generating a digital register input signal including a received preamble portion; a finite state machine for selecting a memory address of the demodulated signal based on the received preamble portion; a preamble memory for storing all possible preambles contained within the demodulated signal and for supplying a selected preamble memory output corresponding to the selected memory address; and a memory alignment module configured to compare phase information of symbols of the preamble portion and preamble phase information of symbols of the selected preamble memory output. This system checks that the preamble portion of the register input signal aligns with the selected preamble memory output and makes corrections when necessary.

Memory misalignment correction

An apparatus includes an antenna that is configured to transmit a radio frequency signal across a transmission media having a channel response impairment. A transmission path includes an encoder circuit that encodes data on a carrier signal; and a pre-equalizer circuit that is configured to pre-distort the encoded data according to equalizer coefficients representing the channel response impairment. A first equalization path includes circuitry that generates the equalizer coefficients based upon transients resulting from a presence change event for the carrier signal. A second equalization path includes circuitry that generates the equalizer coefficients based upon knowledge of encoded data on the carrier signal. Selection circuitry selects between the first equalization path and the second equalization path.

Equalization from presence change transients

An apparatus for detecting the end of a communication is disclosed. The apparatus includes an interface circuit for receiving an encoded signal and a carrier signal recovery circuit coupled to an output of the interface circuit. The carrier signal recovery circuit is configured to output a carrier signal of the encoded signal and a second signal that is out of phase with the carrier signal. The apparatus also includes a decoding circuit configured to decode the encoded signal as a function of both the encoded signal and the carrier signal output by the carrier signal recovery circuit. The apparatus also includes a detection circuit configured to detect an indication of an end of a communication in the encoded signal as a function of both the encoded signal and the second signal.

End of communication detection

A proximity integrated circuit card bias adjustment. In one example, a decoding circuit, having an decoding range, for translating a data-frame signal having an information portion and a bias portion into an output code; and a bias adjust circuit coupled to receive the output code from the decoding circuit, and adjust the bias portion of the data-frame signal such that the output code is within the decoding range is disclosed. In another example, a method for proximity integrated circuit card bias adjustment, comprising: translating a data-frame signal having an information portion and a bias portion into an output code; and adjusting the bias portion of the data-frame signal such that the output code is within a decoding range is disclosed.

Proximity integrated circuit card bias adjustment

A symbol clock recovery circuit comprising an ADC, a controllable inverter and a timing detector. A timing detector input terminal is configured to receive an ADC output signal from an ADC output terminal; a timing detector output terminal is configured to provide a digital output signal; and a first timing detector feedback terminal is configured to provide a first feedback signal to the inverter control terminal. The timing detector is configured to determine an error signal associated with the received ADC output signal, and set the first feedback signal in accordance with the error signal.

Symbol clock recovery circuit

The invention proposes a smart card which comprises a digital signal processing receiver that can automatically identify the type of a smart card reader based on the error vector magnitude of signals received from the reader. The digital signal processing receiver is able to reconfigure itself at runtime in order to optimally minimize its power consumption in dependence on the type of reader it is communicating with. Furthermore, the invention proposes a new preamble structure that comprises a basic part and an optional additional part.

Smart card

Configurable suppression of harmonics in a radio frequency (RF) transmitter circuit having two class-D switching amplifiers that produce a differential output signal having introduced harmonics is contemplated. A selected harmonic is used to determine a time duration. A harmonic suppression circuit modifies a radio frequency polar modulated data signal that is encoded using an amplitude component and a phase component. The modification is responsive to the determined time duration. The switching power amplifiers amplify the modified polar modulated data signal to produce an amplified signal. The amplified signal includes three signal levels, a high signal level, a middle signal level and a low signal level. The timing of transitions between the high and low signal levels represents the phase component, and the transitions include the middle signal level for the time duration, thereby suppressing the selected harmonic.

Harmonic suppression in switching amplifiers

Equalization circuits and methods are implemented for a variety of applications. According to one such application, a transmitting device wirelessly communicates using an antenna. The device has a transmission circuit that is configured and arranged to transmit a first wireless signal using magnetic coupling between the antenna and a remote device, the coupling occurring over a wireless medium. A receiver circuit of the transmitting device is configured and arranged to receive a second wireless signal that is from the antenna and that represents the first wireless signal as modified by the coupling occurring over the wireless medium. An error circuit of the device is configured and arranged to generate an error signal by comparing the first wireless signal to the second wireless signal. An equalizer circuit of the device is configured and arranged to pre-code the first wireless signal with coding that compensates for inter-symbol interference by compensating for the error signal.

Adaptive equalizer and/or antenna tuning

Smart card with reconfigurable receiver

In one embodiment, an apparatus is provided that includes a first circuit configured and arranged to provide a modulated carrier signal in response to a signal provided from the antenna. The modulated carrier signal conveys data using peaks or amplitudes of the carrier signal. A second circuit is configured to rectify the modulated carrier signal and integrate the rectified signal in response to a first clock signal. A third circuit is coupled to an output of the second circuit and is configured to sample the integrated signal values and provide therefrom a sample-based approximation of the modulated carrier signal.

Growing community of inventors

Den Bosch, Netherlands

Massimo Ciacci