Broadcom Corporation

Avago Technologies International Sales Pte. Limited

Stmicroelectronics S.a.

Massimo Brandolini

Leonard Dauphinee

Young J Shin

Ramon Alejandro Gomez

Francesco Gatta

Hanli Zou

Thomas J Kolze

Bruce Joseph Currivan

Loke Kun Tan

Lin He

Robindra B Joshi

Binning Chen

Chun-Ying Chen

Chonghua Zhong

Dongsoo Daniel Koh

Giuseppe Cusmai

Jianhong Xiao

Ray (Ramon) Gomez

Pin-En Su

Tao Wang

Mo Maggie Zhang

Rezaur Rahman Khan

Didier Belot

Kevin Lee Miller

Jiangfeng Wu

Tianwei Li

Francesco Svelto

Wei-Te Chou

Wei Li

Reza Khan

Hans Eberhart

Hemasundar Mohan Geddada

Marco Sosio

Zen-Che Lo

Acer Chou

Shriram Kalusalingam

A method and apparatus for calibrating a pipelined analog-to-digital converter (ADC) is disclosed. A method includes reading a first output level from a first sub-ADC, reading one or more additional output levels from one or more additional sub-ADCs, combining the one or more additional output levels from the one or more additional sub-ADCs into a combined output level, and adjusting a comparator threshold of the first sub-ADC when the first output level and the combined output level meet a set of predetermined conditions.

Pipelined analog-to-digital converter calibration

A method and apparatus for calibrating a CDAC-based analog-to-digital converter is disclosed. In one aspect, a calibration method includes: applying a predetermined pattern of voltages to first plates of a group of N capacitors, wherein N is an integer greater than 1; applying a zero voltage to the second plates of the group of N capacitors, wherein the second plates of the group of N capacitors are connected in common; removing the zero voltage to the second plates of the group of N capacitors; applying a zero voltage to all of the first plates of the group of N capacitors; quantizing a voltage on the second plates of the group of N capacitors; converting the quantized voltage on the second plates of the group of N capacitors to an adjustment value; and loading the adjustment value into a lookup table.

Digital calibration of capacitive mismatches in analog-to-digital converters

Method and apparatuses are disclosed to substantially compensate for various unwanted interferences and/or distortions within a communications receiver. Each of these apparatuses and methods estimate the various unwanted interferences and/or distortions within the communications receiver. Each of these apparatuses and methods remove the estimates of the various unwanted interferences and/or distortions within the communications receiver from one or more communications signals within the communications receiver to substantially compensate for the various unwanted interferences and/or distortions.

Compensating for unwanted interference in a communications receiver

The present disclosure is directed to a system and method for adjusting a conversion speed of an asynchronous SAR ADC based on a margin of time between when a conversion of a sample of an analog signal completes and a next sample of the analog signal is taken, referred to as a 'conversion time margin.' The system and method reduce the conversion speed of an asynchronous SAR ADC when the conversion time margin permits to reduce the amount of power consumed and/or noise produced by the asynchronous SAR ADC.

Adaptive asynchronous SAR ADC

Embodiments provide transmitter topologies that improve the power efficiency and bandwidth of RF transmitters for high transmission power applications. In an embodiment, the common-emitter/source PA of conventional topologies is replaced with a current-input common-base/gate PA, which is stacked on top on an open-collector/drain current-output transmitter. The common-base/gate PA protects the output of the transmitter from large output voltage swings. The low input impedance of the common-base/gate PA makes the PA less susceptible to frequency roll-off, even in the presence of large parasitic capacitance produced by the transmitter. At the same time, the low input impedance of the common-base/gate PA reduces the voltage swing at the transmitter output and prevents the transmitter output from being compressed or modulated. In an embodiment, the DC output current of the transmitter is reused to bias the PA, which results in power savings compared to conventional transmitter topologies.

Wideband power efficient high transmission power radio frequency (RF) transmitter

Systems and methods for switching impedance are provided. In some aspects, a system includes first and second impedance elements and an impedance switch module, which includes a third impedance element coupled between the first and second impedance elements and a switch parallel to the third impedance element. The switch is coupled between the first and second impedance elements, and is configured to switch between an open configuration and a closed configuration. An electrical path is completed between the first impedance element and the second impedance element via the first switch in the closed configuration. The electrical path is not completed in the open configuration. A total impedance of the first impedance element, the second impedance element, and the impedance switch module is varied based on the switching between the open configuration and the closed configuration.

Systems and methods for impedance switching

Systems and methods for demodulating a plurality of contiguous channels contained within a bandlimited portion of a radio-frequency (RF) input signal are provided. In an embodiment, the bandlimited portion of the RF input signal is down-converted to baseband. After down-conversion, the bandlimited portion overlaps at baseband with a mirror image of the bandlimited portion. The plurality of contiguous channels within the down-converted signal similarly overlap at baseband and subsequently occupy a bandwidth substantially equal to half that required before down-converting. Image rejection is performed in the digital domain to recover each of the plurality of overlapping channels.

Variable low IF receiver for multi-channel applications

Selectable interference cancellation in a communications receiver

Highly power efficient transmitter output stage designs are provided. In an embodiment, the probability density function (PDF) of an input signal is divided into a plurality of regions, and samples of the input signal are processed depending on the region of the PDF within which they fall. The PDF can be divided between an inner region corresponding to samples of the input signal that are within a predetermined amplitude range, and outer regions corresponding to samples of the input signal that are outside of the predetermined amplitude range. Samples of the input signal that fall in the inner region are processed by a class A biased amplifier and samples of the input signal that fall in the outer regions are processed by a class B biased amplifier. Output stage designs according to embodiments can be implemented as power amplifiers or power digital-to-analog converters (DACs).

High efficiency output stage amplification for radio frequency (RF) transmitters

A system includes a first storage element to store an input signal for a first sampling lane for a SHA-less stage. A first switch is connected with the first storage element, the first switch to control when the first storage element stores the input signal for sampling on the first sampling lane. A second switch is connected in series with the first switch, the second switch to control an instance for sampling the input signal stored on the first storage element for the first sampling lane.

Time-interleaved skew reduced pipelined analog to digital converter

Compensating for unwanted distortion in a communications receiver

Configurable adaptive filter

Multi-tuner variable low IF receiver for multi-channel applications

Growing community of inventors

Irvine, CA, United States of America

Massimo Brandolini