Micron Technology Incorporated

Massimiliano Turconi

Massimiliano Patriarca

Nicola Del Gatto

Federica Cresci

Angelo Alberto Rovelli

Maddalena Calzolari

Michela Spagnolo

Methods, systems, and devices for event management for memory devices are described. A memory system may include a frontend (FE) queue and a backend (BE). Each queue may include an interface that can be operated in an interrupt mode or a polling mode based on certain metrics. For example, the interface associated with the FE queue may be operated in a polling mode or an interrupt mode based on whether a quantity of commands being executed on one or more memory devices of the memory system satisfies a threshold value. Additionally or alternatively, the interface associated with the BE queue may be operated in a polling mode or an interrupt mode based on whether a quantity of active logical block addresses (LBAs) associated with one or more operations being executed on one or more memory devices of the memory system satisfies a threshold value.

Interrupt mode or polling mode for memory devices

Systems, apparatuses, and methods related to a controller for managing sideband communications are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit can manage a first type of memory device that operates according to a first set of timing characteristics and a second type of memory device that operates according to a second set of timing characteristics. The controller can provide an additional layer of encryption or decryption for sideband communications between the host and the memory devices connected to the controller. The front end portion receives sideband communications through an interface and is stored by a cache memory within the central controller portion which also comprises an auxiliary security component to encrypt the sideband communications. The back end portion provides a route to the memory devices and the management unit applies the encryption or decryption to the sideband communication.

Sideband communication management

Methods, systems, and devices for low latency storage based on data size are described. A memory system may include logic, a processor, a first memory, and a second memory. The logic may be configured to receive commands, or data, or both, from a host system. The first memory and the second memory may be coupled with the processor. The processor may be configured to store, or to cause the storage of, data for commands associated with data that are smaller than a threshold in the first memory and to store data for commands associated with data that are larger than the threshold in the second memory. A first communication path between the logic and the first memory may be associated with a faster transfer speed than a second communication path between the logic and the second memory.

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Gorgonzola, Italy

Massimiliano Turconi