Stmicroelectronics S.r.l.

Semiconductor Components Industries, LLC

Stmicroelectronics Pvt. Ltd.

Other

Stmicroelectronics International N.v.

Massimiliano Picca

Roberto Cardu

Cristian Porta

Lorenzo Trevisan

Stefano Zanardi

Nitin Bansal

Amit Katyal

Joshipura Jwalant

Rino Micheloni

Saverio De Palma

Stefano Casula

Michele Sblano

Giovanni Campardo

Osama Khouri

Roberto Ravasio

Andrea Sacco

Jacopo Mulatti

Maurizio Branchetti

Stefano Commodaro

Mirko Scapin

Francesco Mannino

Stefano Amato

Patrizia Mongelli

According to an aspect, a non-regulated power converter includes a plurality of switching tank converter (STC) modules configured to be connected in parallel and to a load. The plurality of STC modules includes a first STC module configured to generate a first output current and a second STC module configured to generate a second output current. The first STC module includes an output current (OC) measuring circuit configured to measure a value of the first output current, and a dead time (DT) adjustor configured to compare the value of the first output current with a value of a minimum output current provided by the plurality of STC modules. The DT adjustor is configured to adjust a dead time in response to the value of the first output current being greater than the value of the minimum output current.

Non-regulated power converter with current sharing control

A driving module of a resonant converter receives an enabling signal and a voltage across a switch of a secondary side, and generates a control signal for first and second switches of the secondary side. The driving module cyclically controls switches of a primary full-bridge switching stage and both switches of the secondary side. After a fixed time, the driving module turns off the low-side switch and turns on the high-side switch, waits for a rising edge of the enabling signal, waits for zero current in the secondary side switches, turns off the first switch via the control signal after a variable delay relative to the rising edge of the enabling signal, keeps the second switch on, waits for zero voltage across the first switch, switches back on the first switch via the control signal when the voltage measured across the first switch drops below a variable threshold.

Method for driving a resonant converter, and corresponding converter and computer program product

A resonant converter includes a primary switching circuit including a primary winding and upper and lower switching half-bridge circuits alternately activated during switching cycles of the resonant converter responsive to switching control signals. The switching half-bridge circuits each include a phase node to drive the primary winding. A resonance inductor is coupled to the primary winding. A secondary resonant circuit has a secondary winding magnetically coupled to the primary winding and a resonance capacitor electrically coupled to the secondary winding. A driving circuit generates the switching control signals and senses if a voltage on the phase node of one of the upper and lower switching half-bridge circuits is a negative voltage. The driving circuit adjusts the switching control signals for the switching half-bridge circuit to be activated next switching cycle by a shift time reduced each switching cycle until the negative voltage is less than a negligible under-voltage value.

Method for driving a resonant converter, and corresponding device and computer program product

A resonant converter includes a primary switching circuit with a primary winding and a primary full-bridge switching stage that drives the primary winding. A resonance inductor is in series with the primary winding. A secondary resonant circuit has a secondary winding magnetically coupled to the primary winding and a resonance capacitor electrically connected in parallel with the secondary winding. A secondary rectification stage is electrically connected in parallel to the resonance capacitor. A driving module receives a signal representing the voltage measured across an upper or lower switching half-bridge. The drive module detects a negative voltage in the signal. At each cycle, the drive module anticipates a control signal for control of the switches of the lower or upper switching half-bridge that is to be activated the next switching cycle by a shift time that is reduced cycle until the condition of absence of negative voltage in the signal is satisfied.

An area efficient distributed device for integrated voltage regulators comprising at least one filler cell coupled between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size portion of said device is coupled to said I/O rails for distributing portions of said device on the periphery of said chip. The device is coupled as small size portion on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.

Area-efficient distributed device structure for integrated voltage regulators

An area efficient distributed device for integrated voltage regulators comprising at least one filler cell coupled between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size replica of said device is coupled to said I/O rails for distributing replicas of said device on the periphery of said chip. The device is coupled as small size replica on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.

An area efficient distributed device for integrated voltage regulators comprising at least one filler cell connected between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size replica of said device is coupled to said I/O rails for distributing replicas of said device on the periphery of said chip. The device is connected as small size replica on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.

An electrically programmable memory including: an array of a plurality of memory cells arranged accordingly to a NAND architecture, said memory cells grouped into a plurality of memory blocks and each memory block including a plurality of memory pages; means for receiving an address corresponding to a respective memory block; selecting means for selecting the addressed memory block; and means for detecting a failure of the addressed memory block, wherein the means for detecting a failure includes: a plurality of registers, each register corresponding to a respective memory block and storing an indication of the failure of the respective memory block; and means for reading the register corresponding to the addressed memory block in response to the receiving of the address, and wherein the programmable memory further includes at least one redundant memory block of memory cells including a plurality of redundant memory pages, the selecting means selecting the at least one redundant memory block in place of the addressed memory block in response to the reading of the indication of the failure.

Programmable NAND memory

An oscillator system may include an oscillator block having a plurality of inputs and outputting a clock signal, a frequency divider block receiving the clock signal and outputting a divided clock signal, a tuning block receiving the divided clock signal and outputting a comparison signal, and a control block coupled to the tuning block. The control block may receive the comparison signal. The control block may include a configuration block for producing a plurality of outputs for the corresponding inputs of the oscillator block, and an Up/Down counter having outputs applied to the configuration block.

Method for dynamically tuning the clock frequency of an oscillator and corresponding oscillating system

A method and control device is used for testing electronic memory devices. The method comprises loading test data and/or instructions into a control logic circuit portion associated with a matrix array of memory cells and integrated storage circuitry. According to the invention, a test operation control device is used temporarily instead of the control logic, the test operation control device being external of and connected detachably to the memory device. Advantageously, the test operation control device is a matrix cell array external of the memory.

Method and a device for testing electronic memory devices

A method for error control in multilevel memory cells storing a configurable number of bits. The error control is performed using an error-control code which operates, in the encoding phase, on b-bit binary strings made up of k symbols of r-bit data. When the memory cells store a number r of bits, a data symbol is formed only with the data bits stored in a memory cell. When the memory cells store a number s of bits smaller than r, a data symbol is formed with the data bits stored in a memory cell and with r-s bits having a pre-determined logic value, in which the data bits stored in the memory cell are arranged in the least significant part of the data symbol, and the r-s bits having a pre-determined logic value are arranged in the most significant part of the data symbol.

Method for error control in multilevel cells with configurable number of stored bits

An integrated device having a pad receiving, in a standard operative condition, an input signal having a first value and, in a test operative condition, a test voltage having a second value higher than the first value; an input stage connected to the pad and including an electronic component having a first terminal connected to the pad; a third-level detecting stage connected to the pad and supplying a logic third-level signal having a first level in presence of the input signal and a second level in presence of the test voltage; and a selector connected to a second terminal of the electronic component and structured to connect the second terminal to a reference potential in the presence of the first logic level of the third-level signal and to a biasing voltage higher than the reference potential and lower than the second value in the presence of the second logic level of the third-level signal.

Growing community of inventors

Muggiò, Italy

Massimiliano Picca