Qualcomm Incorporated

Atlazo, Inc.

Masoud Ensafdaran

Dinesh Jagannath Alladi

Seyed Arash Mirhaj

Bo Sun

Sameer Wadhwa

Gary John Ballantyne

Lei Sun

Elias Dagher

Kentaro Yamamoto

Hajir Hedayati

Zixiang Yang

Yuhua Guo

Yi Tang

Anand Meruva

Balasubramanian Sivakumar

Yongjian Tang

Bardia Pishdad

Weihua Chen

Salem Emara

Xiaoke Wen

Farsheed Mahmoudi

Monib Ahmed

Tamer Kafafi

The disclosed technology can be used to convert direct-current voltage and current from an input to a different or the same voltage and current at an output. One example direct-current to direct-current (DC-DC) power converter includes a first switch connected between a source voltage and a first side of an inductor, a second switch connected between the first side of the inductor and a ground, a third switch connected between a second side of the inductor and the ground, and a fourth switch connected between the second side of the inductor and a capacitor. The power converter may further include a comparator configured to compare an output voltage at the capacitor to a threshold voltage and based on the result of the comparison selectively activate or deactivate the first, second, third, and fourth switches in a power cycle.

Power management system including a direct-current to direct-current converter having a plurality of switches

Devices, methods, and systems are described that generate process, voltage and temperature tolerant clock generators, which can be used in low power and low cost applications. The clock generators eliminate the need for a crystal oscillator, are simple to implement, and can use a single frequency calibration step to initially tune the frequency to a reference frequency value, and to allow the clock generator to operate in the presence of process, voltage or temperature variations. One example clock circuit includes a voltage-controlled oscillator that provides a clock output, a gain circuit to receive a reference voltage as one input and a changeable voltage on another input. The clock circuit also includes a frequency-to-voltage convertor circuit that receives a reference current and produces the changeable voltage provided to gain circuit, while a ratio of the reference voltage to the reference current is constant.

Process, voltage and temperature tolerant clock generator

Certain aspects of the present disclosure provide methods and apparatus for calibrating time-interleaved analog-to-digital converter (ADC) circuits and generating a suitable signal for such calibration. Certain aspects provide a signal generator for calibrating a time-interleaved ADC circuit having a plurality of channels. The signal generator generally includes a pattern generator configured to receive a periodic signal and to output a bitstream based on the periodic signal and a conversion circuit having an input coupled to an output of the pattern generator and configured to generate a waveform based on the bitstream. The bitstream has a bit pattern with a total number of bits that shares no common factor with a number of the channels and includes a relatively lower frequency component combined with a relatively higher frequency component.

Calibration for time-interleaved analog-to-digital converters and signal generators therefor

Reducing signal dependence for a reference voltage of a CDAC includes: splitting a decoupling capacitor into a plurality of capacitors smaller in size than a size of the decoupling capacitor; isolating at least one of the plurality of capacitors from a sampling buffer coupled to the reference voltage during a conversion phase; and supplying an appropriate amount of charge needed to replenish charge drawn by capacitors in the CDAC at each conversion step using a charge pump to pump in a dummy charge to the CDAC so that resulting configurations of the CDAC draw substantially similar amount of charge for each code change of the each conversion step.

Reducing signal dependence for CDAC reference voltage

One feature pertains to a digitally controlled oscillator (DCO) that comprises a variable capacitor and noise reduction circuitry. The variable capacitor has a variable capacitance value that controls an output frequency of the DCO. The variable capacitance value is based on a first bank capacitance value provided by a first capacitor bank, a second bank capacitance value provided by a second capacitor bank, and an auxiliary bank capacitance value provided by an auxiliary capacitor bank. The noise reduction circuitry is adapted to adjust the variable capacitance value by adjusting the auxiliary bank capacitance value while maintaining at least one of the first bank capacitance value and/or the second bank capacitance value substantially unchanged. Prior to adjusting the variable capacitance value, the noise reduction circuitry may determine that a received input DCO control word transitions across a capacitor bank sensitive boundary.

Devices and methods for reducing noise in digitally controlled oscillators

Growing community of inventors

San Diego, CA, United States of America

Masoud Ensafdaran