Growing community of inventors

Portland, OR, United States of America

Mason B Cabot

Average Co-Inventor Count = 2.88

ph-index = 7

The patent ph-index is calculated by counting the number of publications for which an author has been cited by other authors at least that same number of times.

Forward Citations = 175

Mason B CabotFrank T Hady (16 patents)Mason B CabotMark B Rosenbluth (12 patents)Mason B CabotJohn Beck (9 patents)Mason B CabotSridhar Lakshmanamurthy (1 patent)Mason B CabotRick Coulson (1 patent)Mason B CabotSameer Nanavati (1 patent)Mason B CabotDavid Lawrence Tennenhouse (1 patent)Mason B CabotAnthony S Bock (1 patent)Mason B CabotMason B Cabot (18 patents)Frank T HadyFrank T Hady (49 patents)Mark B RosenbluthMark B Rosenbluth (89 patents)John BeckJohn Beck (9 patents)Sridhar LakshmanamurthySridhar Lakshmanamurthy (52 patents)Rick CoulsonRick Coulson (15 patents)Sameer NanavatiSameer Nanavati (8 patents)David Lawrence TennenhouseDavid Lawrence Tennenhouse (6 patents)Anthony S BockAnthony S Bock (5 patents)
..
Inventor’s number of patents
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Strength of working relationships

Company Filing History:

1. Intel Corporation (18 from 54,750 patents)


18 patents:

1. 11016895 - Caching for heterogeneous processors

2. 10339061 - Caching for heterogeneous processors

3. 9965393 - Caching for heterogeneous processors

4. 9235550 - Caching for heterogeneous processors

5. 9152432 - System and method to accelerate access to network data using a networking unit accessible non-volatile storage

6. 8799579 - Caching for heterogeneous processors

7. 8402222 - Caching for heterogeneous processors

8. 8156285 - Heterogeneous processors sharing a common cache

9. 7991987 - Comparing text strings

10. 7577792 - Heterogeneous processors sharing a common cache

11. 7401184 - Matching memory transactions to cache line boundaries

12. 7360031 - Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces

13. 7302528 - Caching bypass

14. 7266626 - Method and apparatus for connecting an additional processor to a bus with symmetric arbitration

15. 7200713 - Method of implementing off-chip cache memory in dual-use SRAM memory for network processors

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