Micron Technology Incorporated

Masihhur R Laskar

Darwin Franseda Fan

Manuj Nahar

Jeffery B Hull

Hung-Wei Liu

Anish A Khandekar

Ashonita A Chavan

Vassil N Antonov

Irina V Vasilyeva

Albert Liao

Xue-Feng Lin

Fatma Arzum Simsek-Ege

Nicholas R Tapias

Sanjeev Sapra

Jerome A Imonigie

Devesh Dadhich Shreeram

A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.

Vertical transistor, integrated circuitry, method of forming a vertical transistor, and method of forming integrated circuitry

Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

Single-crystal transistors for memory devices

Integrated circuitry comprises an electronic component. Insulative silicon dioxide is adjacent the electronic component. The insulative silicon dioxide has at least one of (a) and (b), where: (a): an average concentration of elemental-form H of 0.002 to 0.5 atomic percent; and (b): an average concentration of elemental-form N of 0.005 to 0.3 atomic percent. Other embodiments, including method, are disclosed.

Integrated circuitry, method used in the fabrication of a vertical transistor, and method used in the fabrication of integrated circuitry

Methods, apparatuses, and systems related to reduction of tapering on a sidewall of an opening are described. An example method includes forming a silicate material comprising a gradient borophosphosilicate glass (BPSG) stack on a semiconductor structure. The example method further includes etching a portion of the silicate material to form an opening within the silicate material having sidewalls, wherein the gradient BSPG stack comprises varying concentrations of boron and phosphorous to reduce tapering of the sidewalls in response to the etching.

Semiconductor structure formation

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Boise, ID, United States of America

Masihhur R Laskar