Intel Corporation

Micron Technology Incorporated

Intel Corproation

Mase J Taub

Kiran Pangal

Sandeep K Guliani

Raymond W Zeng

Kerry Dean Tedrow

Jahanshir J Javanifard

Rajesh Sundaram

Nevil N Gajera

Daniel Chu

Balaji Srinivasan

Rakesh Jeyasingh

Derchang Kau

Bo Li

Koushik Banerjee

Robert E Larsen

Sanjay Rangan

Bharat M Pathak

Dany-Sebastien Ly-Gagnon

Lark-Hoon Leem

John Gorman

Sandeepan Dasgupta

Xin Guo

Zion S Kwok

Andrew W Vogan

Paul D Ruby

Prashant S Damle

Nathan Franklin

Gerald J Barkley

Neal R Mielke

Owen W Jungroth

Sanjay S Talreja

Hanmant Pramod Belgal

Christopher John Haid

Ning Wu

Vishram P Dalvi

Chaitanya S Rajguru

Hemant P Rao

Marc E Landgraf

Jeff Evertt

Kenneth E Wojciechowski

Binh N Ngo

Cesar Galindo

Edward M Babb

Ashir G Shah

Bi Han

Rupinder K Bains

Marcus E Landgraf

Ivan Kalastirsky

Xin Liu

Jahanshir J Jayanifard

A read technique for both SLC (single level cell) and MLC (multi-level cell) cross-point memory can mitigate drift-related errors with minimal or no drift tracking. In one example, a read at a higher magnitude voltage is applied first, which causes the drift for cells in a lower threshold voltage state to be reset. In one example, the read at the first voltage can be a full float read to minimize disturb. A second read can then be performed at a lower voltage without the need to adjust the read voltage due to drift.

Cross-point memory read technique to mitigate drift errors

A memory device including a memory array and address lines; and decoder circuitry to apply a first bias to a WL coupled to a memory cell selected for a memory operation, a second bias to a BL coupled to the selected memory cell, and one or more neutral biases to the other BLs and WLs of the memory array; wherein the decoder circuitry comprises a plurality of bias circuits coupled to the address lines, a first bias circuit of the plurality of bias circuits comprising a transistor pair and an additional transistor coupled to an address line of the plurality of address lines, wherein the bias circuit is to apply, to the address line, the first bias through the transistor pair in a first state, the second bias through the transistor pair in a second state, and the neutral bias through the additional transistor in a third state.

Bipolar decoder for crosspoint memory

Methods, systems, and devices for a modified write voltage for memory devices are described. In an example, the memory device may determine a first set of memory cells to be switched from a first logic state (e.g., a SET state) to a second logic state (e.g., a RESET state) based on a received write command. The memory device may perform a read operation to determine a subset of the first set of memory cells (e.g., a second set of memory cells) having a conductance threshold satisfying a criteria based on a predicted drift of the memory cells. The memory device may apply a RESET pulse to each of the memory cells within the first set of memory cells, where the RESET pulse applied to the second set of memory cells is modified to decrease voltage threshold drift in the RESET state.

Modified write voltage for memory devices

A method, apparatus and system to address memory cells in a memory array that includes address lines comprising wordlines (WLs) and bitlines (BLs). The method comprises: controlling a decoder circuitry of a memory array, the memory array including a plurality of WLs and a plurality of BLs, the decoder circuitry including a plurality of switches coupled respectively to the WLs, or respectively to the BLs; and causing a selected switch of the plurality of switches to change a bias of a corresponding selected address line coupled thereto from a floating bias at an idle state of the decoder circuitry to either a positive bias or a negative bias without changing a bias at deselected address lines corresponding to deselected switches of the plurality of switches from the floating bias at the idle state.

Device, system and method to float a decoder for deselected address lines in a three-dimensional crosspoint memory architecture

Nonvolatile memory (e.g. phase change memory) devices, systems, and methods that minimize energy expenditure and wear while providing greatly improved error rate with respect to marginal bits are disclosed and described.

Dual demarcation voltage sensing before writes

The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.

Cross point memory control

A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.

Cross-point memory single-selection write technique

Nonvolatile memory (e.g. phase change memory) devices, systems, and methods of programming the nonvolatile memory including sensing of a snapback current using a set demarcation voltage for set bit mapped cells and a reset demarcation voltage for reset bit mapped cells before selective writes.

In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.

Method and apparatus for multi-level setback read for three dimensional crosspoint memory

Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.

Techniques to mitigate bias drift for a memory device

Growing community of inventors

Folsom, CA, United States of America

Mase J Taub