Fujitsu Corporation

Masazumi Maeda

Yoshiharu Yoshizawa

Masahiro Ise

Noriyuki Tokuhiro

Yoshito Koyama

Koji Migita

Kazuko Higurashi

An apparatus for memory control includes a data storage area configured to store data indicative of a distribution of total current consumption required for a write operation as measured with respect to one or more nonvolatile memory devices of a first type, and a control apparatus configured to evaluate, based on the data indicative of the distribution, a degree to which a total amount of current consumption required for a write operation with respect to a memory area in a nonvolatile memory device of the same first type, regarding a current flowing from a power supply to the nonvolatile memory device during the write operation, is deviated toward larger total current consumptions in the distribution, thereby determining whether the memory area is satisfactory.

Apparatus for memory control

A memory controller includes a memory that stores therein data corresponding to a distribution of write durations measured from a nonvolatile memory device of a specific model, and a processor that measures a write duration taken to write data to a memory cell in a nonvolatile memory device of a same model as the specific model and that determines whether or not the memory cell is defective by evaluating, based on the data corresponding to the distribution, a displacement of the measured write duration from a center portion of the distribution.

Memory controller, information processing system, and nonvolatile-memory defect determination method

A memory control circuit includes an input circuit that receives data to be written to a storage having multiple nonvolatile memory cells, and a control circuit, when a second number of bits that are included in a first bit string and having a first number of bits and have a second logical value different from a first logical value equal to initial values stored in the multiple nonvolatile memory cells is equal to or smaller than a first threshold, writes the first bit string and the first additional value to the storage, and that associates, when the second number of the bits is larger than a second threshold larger than the first threshold, a second bit string obtained by reversing logical values of all the bits of the first bit string with a second additional value and writes the second bit string and the second additional value to the storage.

Memory control circuit, memory, and memory control method

An apparatus includes first and second circuits that transmit and receive information to and from each other through first paths, where each of the first and second circuits includes second paths respectively coupled to the first paths, and matrix switches that are provided across the second paths and switch a transmission path of information transmitted to any one of the second paths. Upon detecting an error in the second paths, the apparatus conducts a loop-back test in which each matrix switch is switched to a loop-back state in which information to be transmitted to the second path in which the error has been detected, is looped back. Upon detecting an error in the loop-back test, the apparatus switches the matrix switches to a bypass state in which the second path in which the error is detected is bypassed to another one of the second paths to continue the loop-back test.

Apparatus and method to determine plural locations in communication circuits at which failures have occurred

A delay circuit includes: a delay line that delays an input signal in accordance with a delay setting signal and performs output of the input signal as a delayed signal; and a logic circuit processes the input signal to the delay line and the delayed signal.

Test method of delay circuit including delay line

A control circuit that controls a memory including a storage region and a redundant region, the control circuit includes a detector that detects a defective block in the memory, and a controller that switches, when the detector has detected the defective block, a data storage scheme of the first block detected as the defective block from a first storage scheme to a second storage scheme in which the number of bits of data to be stored in each of memory elements is smaller than the number of bits of data to be stored in each of the memory elements in the first storage scheme, and that stores a portion of data stored in the first block in the first storage scheme to be stored in the first block in the second storage scheme.

Control circuit, semiconductor storage device, and method of controlling semiconductor storage device

A memory includes a memory cell including a memory transistor in which electric charges are stored in an electric charge storage layer when data is written to the memory cell, and a controller configured to control a voltage to be applied to the memory transistor in a predetermined hold time until an amount of electric charges stored in the electric charge storage layer decreases to an amount of electric charges corresponding to a state where the data is erased from the memory cell.

Memory and memory control method

An electronic device includes: a voltage controlled delay line including delay elements configured to delay an input clock signal and output the clock signal, a delay control element configured to control a delay time of the clock signal delayed by the delay elements in accordance with a control voltage, a delay sensitivity adjustment circuit configured to adjust a ratio of an amount of change of the delay time to an amount of change of the control voltage, and a plurality of delay circuits; and a control voltage generation circuit configured to compare a phase of an output signal of any one of the plurality of delay circuits and a phase of the clock signal, generate the control voltage so as to match the phase of the output signal and the phase of the clock signal based on the comparison result, and output the control voltage to the delay control element.

Electronic device and information processing apparatus

A delay circuit comprises a plurality of delay buffers each including two or more serially connected delay units, each of the delay units being capable of variably controlling a delay amount; a variable control voltage generator circuit configured to supply, to a first delay unit included in each of the plurality of delay buffers, a variable control voltage provided to control the delay amount of the first delay unit; and a fixed control voltage generator circuit configured to supply, to a second delay unit included in each of the plurality of delay buffers, a fixed control voltage among a plurality of fixed control voltages for controlling the delay amount of the second delay unit. The plurality of delay buffers are connected in series and an input signal propagates through the plurality of serially connected delay buffers.

Delay circuit, delay locked loop circuit including delay circuit and processor including delay locked loop circuit

An electronic component includes: a first amplifier configured to amplify one of differential signals; a second amplifier configured to amplify another one of the differential signals; a sensor configured to measure voltages of a first output signal outputted from the first amplifier and a second output signal outputted from the second amplifier; and a controller configured to control, based on the voltages measured by the sensor, either one or both of a current and a resistance value of the first amplifier so that a common voltage of the first output signal and a common voltage of the second output signal are approximate to each other.

Electronic component, information processing apparatus, and electronic component control method

A power supply voltage output circuit includes: a power supply voltage generation unit generating a power supply voltage to be supplied into a ring oscillator; a reference clock oscillator oscillating a reference clock with respect to a clock oscillated by the ring oscillator; a phase difference detection unit detecting a phase difference between the clock from the ring oscillator and the reference clock from the reference clock oscillator; a filter unit smoothing an output of the phase difference detection unit; and a PWM signal generation unit generating a PWM signal based on an output of the filter unit such that the phase difference approaches zero.

Power supply voltage output circuit

A variable delay circuitincludes: a multistage delay circuitconstructed by connecting delay elements Dto Dn in series; a selecting unitwhich selects one delayed signal obtained by introducing different amounts of delay by passing a reference clock through one or more of the delay elements Dto Dn; a decision unitwhich, at decision timing synchronized to the reference clock, makes a decision on the logic state of each delayed signal sequentially selected from among the plurality of delayed signals; and a changing point detection unitwhich detects at least two delay elements Dm and Dk where a change has occurred in the logic state of the reference clock at the decision timing, and wherein the difference (k&#x2212;m) between the numbers of delay elements through which the clock signal has passed until reaching one of the two detected delay elements Dm and Dk is used as the number of delay elements that provides a desired delay time.

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Yokohama, Japan

Masazumi Maeda