Nec Corporation

Masayuki Yojima

Tohru Tsujide

Kazuo Nakaizumi

Masao Kinoshita

The present invention provides a semiconductor wafer tester including a substrate, at least one chip mounted on an upper surface of the substrate, the chip having function as a tester, the chip being electrically connected to a contact formed on a lower surface of the substrate through an internal wiring formed in the substrate, and a contact film having at least one first bump formed on an upper surface thereof and at least one second bump formed on a lower surface thereof, the first bump being electrically connected to the second bump through an internal wiring formed throughout the contact film, the contact film being to be disposed to be sandwiched between the substrate and a semiconductor wafer to be tested so that the first bump is in electrical contact with the contact of the substrate and the second bump is in electrical contact with the semiconductor wafer. The tester makes it possible to carry out high frequency test concurrently for a plurality of semiconductor wafers in a shorter period of time with lower costs.

Apparatus for testing semiconductor wafer

In a signal processing circuit, a height arithmetic circuit obtains a measured value of a height of an object by using the principle of triangulation from a second light receiving signal which is transmitted from a second photodetector of position detecting type thereto. An error arithmetic circuit acquires a measurement error by using the principle of triangulation from a first light receiving signal which is transmitted from a first photodetector of position detecting type thereto. A correction circuit calculates a correct height of the object by subtracting an output signal of the error arithmetic circuit from an output signal of the height arithmetic circuit.

Growing community of inventors

Tokyo, Japan

Masayuki Yojima