Toshiba Memory Corporation

Kioxia Corporation

Kabushiki Kaisha Toshiba

Masayuki Usuda

Hiroo Yabe

Masashi Nakata

Hidefumi Kushibe

Hiroyuki Ideno

A voltage generation circuit includes a first input terminal at a power supply voltage, a second input terminal at a reference voltage, an output terminal, a resistor circuit, and a capacitor circuit. The resistor circuit includes resistors connected in series between the first and second input terminals and switching elements connected between the output terminal and a respective one of a plurality of nodes. The capacitor circuit includes a plurality of capacitors, each of which has a first terminal to which a first voltage or a second voltage is applicable and a second terminal connected to the output terminal. The first voltage or the second voltage is selectively applied to the first terminals of the capacitors in accordance with a target value of an output voltage.

Voltage generation circuit and interface circuit

A power supply circuit of a semiconductor device includes a voltage generation circuit, first and second terminals, and a switch circuit. The voltage generation circuit is configured to generate an operation voltage of the semiconductor device. The first terminal is configured to be at a reference voltage corresponding to an external power supply voltage that is supplied from an external source external to the semiconductor device. The second terminal is connectable to a measuring device. The switch circuit is configured to cause one of the operation voltage and the reference voltage to be output toward the second terminal and then the other of the operation voltage and the reference voltage to be output toward the second terminal.

Power supply circuit of semiconductor device, semiconductor device having the same, and method for adjusting operation voltage of device

A voltage regulator includes an operational amplifier that compares a feedback voltage that is proportional to an output voltage and a predetermined reference voltage that corresponds to a desired output voltage. The operational amplifier controls the conduction state of an output transistor according to the comparison. A detecting circuit monitors the operating state of the operational amplifier, and in the case that the operational amplifier is not operating, outputs a signal which causes the output transistor to be placed in a non-conductive state.

Voltage regulator

A latch circuit includes first and second NAND circuits and first and second capacitive elements. The first NAND circuit has a first input node into which a first signal is input. The second NAND circuit has a first input node into which a second signal is input, a second input node which is connected to an output node of the first NAND circuit, and an output node which is connected to a second input node of the first NAND circuit. The first capacitive element has one end connected to the first input node of the first NAND circuit and has another end connected to the output node of the first NAND circuit. The second capacitive element has one end connected to the first input node of the second NAND circuit and has another end connected to the output node of the second NAND circuit.

Latch circuit and comparator circuit

According to one embodiment, a skew correcting device includes a skew calculation circuit and a sampling timing correction circuit. The skew calculation circuit calculates a skew between data and a strobe signal based on sampling values obtained by sampling, at a cycle one half of or shorter than one half of a cycle of the strobe signal, the data and the strobe signal respectively based on a same clock. The sampling timing correction circuit corrects the sampling timing of the data based on the skew calculated by the skew calculation circuit.

Reception circuit

A communication device includes a timing generation circuit generates timing signals at several timing points within one period of a first clock signal. A clock sampling circuit receives the first clock signal and detects a logic level of the first clock signal at each of the timing points. A control circuit calculates a difference between the number of times a first or a second logic level is detected for the first clock signal and outputs a control signal indicating whether a duty ratio of the first clock signal is to be adjusted. A correction circuit that changes at a duty ratio of a second clock signal transmitted to the transmitting device, the duty ratio being set in accordance with the control signal. The duty ratio of the first clock signal is then adjusted by the transmitting device according to the duty ratio of the second clock signal.

Receiving device

According to one embodiment, an integrated circuit is formed on a semiconductor chip, a regulator supplies power to the integrated circuit via the power-supply wire, a first resistor is connected between the first pad electrode and the power-supply wire on the semiconductor chip, and a second resistor is connected between the second pad electrode and the power-supply wire on the semiconductor chip and has a resistance smaller than that of the first resistor.

Growing community of inventors

Tokyo, Japan

Masayuki Usuda