Marvell International Limited

Marvellworld Trade Ltd.

Masayuki Urabe

Akio Goto

Chi Kong Lee

Tony Yoon

Saeed Azimi

Systems, methods and computer program products for programming data into a multi-plane memory device employ a multi-plane data order. To allow multiple data pages to be programmed without a need to increase the size of page buffers, in some implementations, a data transfer scheme at which the data pages are programmed can be manipulated. Specifically, data across all channels can first be programmed into a first plane of the multi-plane flash memory device in parallel. While the data transfer program operation is in progress, data to be programmed into a succeeding plane (e.g., plane '1') can be read into and cached in one or more page buffers. After the data transfer program for the first plane is complete, data cached in the page buffers can be immediately latched and programmed into the multi-plane flash memory device.

Multi-plane data order

In some implementations, an apparatus includes a first programmable hardware timer that specifies an initial wait time before issuing two or more commands to a storage device, and a second programmable hardware timer that specifies an interval time between at least two commands of the two or more commands.

Storage device command interval controller

A method includes, in at least one aspect, asserting a control signal to one or more devices, determining an initial wait time after asserting the control signal, issuing a first command based on the initial wait time, determining a first interval time associated with the first command and a second command, and issuing the second command based on the first interval time.

Flash memory controller

Methods, systems and computer program products for implementing a polling process among one or more flash memory devices are described. In some implementations, the polling process may include sending a read status command to a flash memory device to detect the ready or busy state of the flash memory device. A status register may be included in the flash memory device for storing a status signal indicating an execution state of a write (or erase) operation. A solid state drive system may perform the polling process by reading the status register of the flash memory device.

A system including a plurality of NAND flash memory devices each having a NAND flash interface, where the NAND flash interface of each NAND flash memory device includes an 8-bit data bus, and a memory controller configured to exchange data with the plurality of NAND flash memory devices via the 8-bit data bus. The memory controller is further configured to select a first NAND flash memory device of the plurality of NAND flash memory devices, without using a Chip Enable signal of the NAND flash interface, by transmitting, on the 8-bit data bus, an identification byte identifying the first NAND flash memory device. The memory controller is further configured to transmit, on the 8-bit data bus, a command byte to the first NAND flash memory device. The first NAND flash memory device is configured to perform an operation indicated by the command byte.

Flash memory controller and methods of programming and reading flash memory devices using the controller

A semiconductor device including an electronic circuit, a memory, and an error detecting module. The electronic circuit is configured to receive an input signal having been generated by a test module, and generate an output signal based on the input signal. The memory is configured to store a predetermined output value that is expected to be output from the electronic circuit based on the electronic receiving the input signal, wherein the predetermined output value is stored in the memory prior to the input signal being generated by the test module. The error detecting module is configured to (i) generate a sample value of the output signal, (ii) compare the sample value of the output signal to the predetermined output value stored in the memory, and (iii) generate a result signal that indicates whether the sample value of the output signal matches the predetermined output value.

Method and apparatus for testing an electronic circuit integrated with a semiconductor device

An embedded processor system including a flash process semiconductor die and a digital process semiconductor die. The flash process semiconductor die includes i) first cache memory configured to cache information associated with an embedded processor, and ii) a first cache controller configured to control the first cache memory. The digital process semiconductor die includes i) a translator configured to translate the information between the flash process semiconductor die and the digital process semiconductor die, and ii) the embedded processor. The embedded processor is configured to process the information.

Flash memory module

A device includes a first semiconductor die. Nonvolatile memory stores information associated with a second semiconductor die. Cache memory caches a portion of the information. A cache controller controls the cache memory. A device interface communicates the information to the second semiconductor die. On the second semiconductor die, a semiconductor circuit processes the information stored on the first semiconductor die.

A semiconductor device that includes a module under test that is integrated with the semiconductor device, that receives an input signal from a test module, and that provides an output signal to at least one output terminal based on the input signal. An error detecting module is integrated with the semiconductor device, samples values of the output signal, and outputs the sampled values to the test module.

Method for at speed testing of devices

A memory storage device connectable to a bus comprises a first memory module that stores data, a second memory module that is capable of being programmed, and a memory controller that communicates with the first memory module, the second memory module, and the bus, and that determines an address mapping of selected areas of the first memory module onto the second memory module. When the memory controller receives an access request from the bus, the memory controller accesses data from the first memory module unless the address mapping specifies that the access request maps to the second memory module, whereupon the memory controller accesses replacement data from the second memory module.

Device with mapping between non-programmable and programmable memory

A device is fabricated on a flash process semiconductor die. The device includes main memory to store processor information. A cache memory caches a portion of the processor information. A cache controller controls the cache memory. A device interface communicates the processor information to another semiconductor die. Control logic controls the device interface.

A device is fabricated on a flash process semiconductor die. Main memory stores processor information. A cache memory caches a portion of the processor information. A cache controller controls the cache memory. A device interface communicates the processor information to another semiconductor die. Control logic controls the device interface.

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Isehara, Japan

Masayuki Urabe