Renesas Electronics Corporation

Nec Corporation

Nec Electronics Corporation

Masayuki Terai

Motofumi Saitoh

Munehiro Tada

Kiyotaka Imai

Hirohito Watanabe

Hiroshi Sunamura

Naohiko Kimizuka

Yukishige Saito

Akio Toda

Toshiyuki Iwamoto

Masaharu Matsudaira

Yuri Masuoka

Shinji Fujieda

Yuko Yabe

Kouji Masuzaki

Tomonori Sakaguchi

Koichi Yako

Yukihiro Sakotsubo

A resistance change nonvolatile memory device, includes: a first wiring; an interlayer insulating layer formed over the first wiring; and a second wiring formed over the interlayer insulating layer, wherein the interlayer insulating layer is interposed between the first wiring and the second wiring and includes a hole having a width not greater than a width of the first wiring, wherein the resistance change nonvolatile memory device further includes a lower electrode formed at a bottom portion of the hole and contacting the first wiring; a resistance change layer formed on the lower electrode; and an upper electrode formed over the resistance change layer, wherein the lower electrode, the resistance change layer, and the upper electrode are formed inside the hole, wherein an entirety of the resistance change layer is disposed inside the hole.

Resistance change nonvolatile memory device, semiconductor device, and method of manufacturing resistance change nonvolatile memory device

A resistance change memory has a resistance change device and a control circuit for controlling application of voltage to the resistance change device. The resistance change device has a first electrode, a second electrode, and a resistance change layer interposed between the first electrode and the second electrode. A material for the second electrode includes one of members selected from the group consisting of W, Ti, Ta, and nitrides thereof. During forming of the resistance change device, the control circuit performs a second forming treatment succeeding to a first forming treatment. The first forming treatment includes application of voltage such that the potential of the first electrode is higher than the potential of the second electrode. The second forming treatment includes application of voltage such that the potential of the second electrode is higher than the potential of the first electrode.

Resistance change memory and forming method of the resistance change device

A memory cell is included which has a selection transistor and a variable resistance device connected to a bit line through the selection transistor. The variable resistance device includes a first electrode which has a first metal material and is connected to the selection transistor, a second electrode which has a second metal material different from the first metal material, and an insulating film which is provided between the first electrode and the second electrode, has a third metal material different from the first metal material and the second metal material, and has oxygen. The second metal material has a greater normalized oxide formation energy than the first metal material.

Semiconductor device including a variable resistance device, and method of controlling the semiconductor device

To provide a resistance change nonvolatile memory device performing a stable switching operation at a low cost. The resistance change nonvolatile memory device has a first wiring, an interlayer insulating layer formed thereon, a second wiring formed thereon, and a resistance change element formed between the first wiring and the second wiring. The interlayer insulating layer between the first wiring and the second wiring has a hole having a width not greater than that of the first wiring. The resistance change element is in contact with the first wiring and has a lower electrode at the bottom of the hole, a resistance change layer thereon, and an upper electrode thereon. They are formed inside the hole. The first wiring contains copper and the lower electrode contains at least one metal selected from the group consisting of ruthenium, tungsten, cobalt, platinum, gold, rhodium, iridium, and palladium.

In a case where a DRAM and a ReRAM are mounted together, a manufacturing cost thereof is reduced while maintaining performance of a capacitance element and a variable resistance element. A semiconductor memory device includes a variable resistance element and a capacitance element. The variable resistance element has a cylinder type MIM structure with a first depth, and is designed for a variable resistance type memory. The capacitance element has a cylinder type MIM structure with a second depth deeper than the first depth, and is designed for a DRAM.

Semiconductor memory device, semiconductor device and method of manufacturing semiconductor memory device

Provided is a semiconductor device including: a memory cell having a variable resistance device; and a control unit that controls a voltage applied to the memory cell, wherein the variable resistance device includes a lower electrode contains a first metal material, an upper electrode containing a second metal material, and an insulating film containing oxygen, the first metal material has a normalized oxide formation energy higher than that of the second metal material, and the control unit applies a positive voltage to the upper electrode at the time of an operation of increasing a resistance value of the insulating film and an operation of decreasing the resistance value thereof, and applies a positive voltage to the lower electrode at the time of an operation of reading out the resistance value of the insulating film.

Semiconductor device and method of controlling semiconductor device

A resistance change nonvolatile memory device includes with a first electrode, a resistance change portion provided on the first electrode, and a second electrode provided on the resistance change portion. The resistance change portion is equipped with a resistance change layer provided on the first electrode and undergoing a change in resistance with an applied voltage and a stable layer provided on the resistance change layer and forming a filament. The resistance change layer and the stable layer are made of metal oxides different from each other. The oxide formation energy of the resistance change layer is higher than that of the stable layer. The resistance change layer has such a film thickness as to permit the resistance of the resistance change portion in an Off state to fall within a range determined by the film thickness.

Resistance change nonvolatile memory device, semiconductor device, and method of operating resistance change nonvolatile memory device

A semiconductor device includes at least first and second electrodes, and a layer including a transition metal oxide layer sandwiched between the first and second electrodes. The transition metal oxide layer includes first and second transition metal oxide layers formed of different first and second transition metals, respectively. The first transition metal oxide layer is provided on the first electrode side, the second transition metal oxide layer is provided on the second electrode side, the first transition metal oxide layer and the second transition metal oxide layer are in contact with each other, the first transition metal oxide layer has an oxygen concentration gradient from the interface between the first transition metal oxide layer and the second transition metal oxide layer toward the first electrode side, and the oxygen concentration at the interface is greater than the oxygen concentration on the first electrode side.

Semiconductor device with variable resistance element and method for manufacturing the same

In the trap type memory chip the withstanding voltage is raised up, and then the electric current for reading out is increased. There are formed on the p-type semiconductor substratea first gate lamination structure which comprises a first insulating filmincluding a trap layer, and a first conductive body, and a second gate lamination structure which comprises a second insulating filmfree of a trap layer and including an insulating film layerdoped with metal for controlling the work function at least on the upper layer, and a second conductive body. A source drain regionand a source drain regionare formed such that the first gate lamination structure and the second gate lamination structure are interleaved therebetween. The effective work function of the second gate lamination structure is higher than that of the first gate lamination structure.

Semiconductor device

A semiconductor storage device is provided for solving the problem of the inability to simultaneously realize high reliability and decreased cell area. A selection electrode () is formed to sandwich an insulating film () with a p-type semiconductor region (). A first n-type semiconductor region () and a second n-type semiconductor region () are formed in the p-type semiconductor region () at two sides of the selection electrode (). A first resistance-changing layer () is connected to the first n-type semiconductor region (), and a second resistance-changing layer () is connected to the second n-type semiconductor region (). In addition, a first wiring layer () is connected to the second resistance-changing layer (), and a second wiring layer () is connected to the second resistance-changing layer ().

Semiconductor storage device, memory cell array, and a fabrication method and drive method of a semiconductor storage device

Nonvolatile memory device

A channel is formed at a recessed portion or a projecting portion of a substrate, and a gate insulating film is formed so as to have first to third insulating regions along the channel. Each of the gate insulating films of the first and third insulating regions has a first gate insulating film containing no electric charge trap formed on a plane different from a principal surface of the substrate, an electric charge accumulating film containing an electric charge trap, and a second gate insulating film containing no electric charge trap. The gate insulating film of the second insulating region at the middle is formed on a plane parallel to the principal surface of the substrate and is composed of only a third gate insulating film containing no electric charge trap.

Semiconductor device, and its manufacturing method

Provided is a semiconductor device including: source-drain regions formed on a silicon substrate with a channel forming region sandwiched therebetween; a word gate electrode formed on the channel forming region via a word gate insulating film not including a charge storage layer; a control gate formed on the silicon substrate on one side of the word gate electrode via a trap insulating film including a charge storage layer; and a control gate formed on the silicon substrate on the other side of the word gate electrode via a trap insulating film including a charge storage layer. A bottom of the word gate electrode is made to be higher than the control gate and a bottom of the control gate, and a level difference between the bottoms of the electrodes is made to be larger than a physical film thickness of the word gate insulating film.

Disclosed is a semiconductor storage device comprising a semiconductor substrate, a first and a second impurity diffusion layer formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a first gate electrode formed on the semiconductor substrate via the gate insulating film. The gate insulating film has a nitrogen-containing silicon oxide film inside, and a silicon oxide film is so arranged on both sides of the nitrogen-containing silicon oxide film as to sandwich the nitrogen-containing silicon oxide film. In addition, the nitrogen composition in the nitrogen-containing silicon oxide film is increased from the semiconductor substrate side to the first gate electrode side.

Semiconductor memory device, method of driving the same and method of manufacturing the same

There is provided a trap memory device suppresses electric charges from flowing from the outside into a charge accumulation region and accumulated electric charges from diffusing to the outside or flowing out due to a defect. A gate conductoris formed through a laminate insulating film including a first gate insulating film, a charge accumulation layerand a second gate insulating filmon a silicon substrate. The laminate insulating film (to) projects outside the gate conductorand extends to under the outer end of a side wall. The charge accumulation layerincludes a high trap surface-density regionimmediately under the gate conductor and a low trap surface-density regionoutside the gate conductor.

Growing community of inventors

Tokyo, Japan

Masayuki Terai