Fujitsu Corporation

Fujitsu Vlsi Limited

Masayuki Takeshige

Sumitaka Hibino

Kenji Yamada

Kazuya Taniguchi

Kunihiro Ohara

Toshiyuki Nishii

Yukisato Miyazaki

Hiroshi Naritomi

Hayato Isobe

Teruyoshi Kondo

Tetsuji Tsutsumi

Method and system for shortening the time needed to test a semiconductor device having a plurality of memory circuits. The semiconductor device includes an address decoder for selecting a plurality of memory circuits and causing the memory circuits to perform a read/write operation. A comparator receives plural pieces of read data read from the plurality of memory circuits and compares the plural pieces of read data with one another. A processing unit compares one of the plural pieces of read data with write data. Using the comparison results of the comparator and the processing unit shorten the time needed to test the plurality of memory circuits.

Test method and test system for semiconductor device

A processor for performing calculations based on an instruction code, the number of bits of which is not an integer multiple of a byte. The instruction code is divided into higher order bits and lower order bits. The number of the lower order bits is an integer multiple of one byte. A memory stores the lower order bits in a lower order bit storage section and the higher order bits in a higher order bit storage section. The lower order bits and the corresponding higher order bits are read from the memory in the same cycle when generating the instruction code.

Method and apparatus for compactly storing instruction codes

A memory having a plurality of memory cells and a plurality of redundant memory cells accesses a redundant memory cell in lieu of a failed memory cell. The memory is tested for failed memory cells. Addresses of detected failed memory cells are stored in a first set of registers, and addresses of redundant memory cells are stored in a second, corresponding set of registers. An external address is compared with the address stored in the first set of registers and if there is a match, the corresponding redundant memory cell address stored in the second register set is used to access the memory, in lieu of the external memory address.

Method of replacing failed memory cells in semiconductor memory device

An apparatus and method for transferring digital data is herein disclosed using a central processing unit and a direct memory access controller. Based on the control of the central processing unit, a direct memory access controller counts the number of words stored in a memory device by determining the number and position of the bytes contained in the words comprising the data to be transferred.

Method and apparatus for determining the number of words of transferred

Growing community of inventors

Kasugai, Japan

Masayuki Takeshige