Sharp Kabushiki Kaisha Corporation

Masayuki Tajiri

Takashi Nakano

Shinobu Yamazaki

Shigeo Ohnishi

Naoyuki Shinmura

Tetsuya Ohnishi

Toyohiro Harazono

Takahiro Shibuya

Takayoshi Hashimoto

Hisashi Yonemoto

Nobuyoshi Awaya

Kohji Inoue

Atsushi Shimaoka

Provided is a switching element that is hardly destroyed even under a high bias condition in an off state because an electric field near a gate electrode is relaxed. A switching elementincludes a carrier transit layer, a carrier supply layerformed on an upper surface of the carrier transit layer, having a wider bandgap than the carrier transit layer, and forming a heterojunction with the carrier transit layer, a source electrode, a drain electrode, and a gate electrodearranged between the source electrodeand the drain electrode. An impurity-doped layeris interposed between the carrier transit layerand the drain electrode. The impurity-doped layeris formed as a semiconductor layer by heavily doping an impurity having the same conductivity type as a carrier constituting a two-dimensional carrier gas layergenerated due to the heterojunction, and a depletion layeris formed in the impurity-doped layerwhen the switching elementis in the off state, and thereby a high electric field generated near the gate electrodeis dispersed.

Switching element

Provided is a switching element capable of effectively preventing a collapse phenomenon. A switching element () includes an electron running layer (), an electron supplying layer () formed on an upper surface of the electron running layer (), having a band gap larger than that of the electron running layer (), and forming a heterojunction with the electron running layer (), a recombination layer () formed on an upper surface of the electron supplying layer () and having a band gap smaller than that of the electron supplying layer (), a source electrode () and a drain electrode () at least partially formed on the upper surface of the electron running layer (), and a gate electrode () at least partially formed on the upper surface of the electron supplying layer () and arranged between the source electrode () and the drain electrode (). When the switching element () is in an off state, electrons and holes are recombined in the recombination layer ().

Switching element utilizing recombination

A semiconductor device comprising at least two wiring layers on a substrate or a surface layer of the substrate, wherein a lower wiring layer of the two wiring layers contains silicon, and a silicon carbide layer is placed between the lower wiring layer and an upper wiring layer.

Semiconductor device and method for producing the same

A formation method of an element isolation film according to which a high-voltage transistor with an excellent characteristic can be formed is provided. On a substrate, a gate oxide film is previously formed. A CMP stopper film is formed thereon, and thereafter, a gate oxide film and a CMP stopper film are etched. The semiconductor substrate is etched to form a trench. Further, before the trench is filled with a field insulating film, a liner insulating film is formed at a trench interior wall, and a concave portion at the side surface of the gate oxide film under the CMP stopper film is filled with the liner insulating film. In this manner, formation of void in the element isolation film laterally positioned with respect to the gate oxide film can be prevented.

Semiconductor device manufacturing method and semiconductor device

A formation method of an element isolation film according to which a high-voltage transistor with an excellent characteristic can be formed is provided. On a substrate, a gate oxide film is previously formed. A CMP stopper film is formed thereon, and thereafter, a gate oxide film and a CMP stopper film are etched. The semiconductor substrate is etched to form a trench. Further, before the trench is filled with a field insulating film, an liner insulating film is formed at a trench interior wall, and a concave portion at the side surface of the gate oxide film under the CMP stopper film is filled with the liner insulating film. In this manner, formation of void in the element isolation film laterally positioned with respect to the gate oxide film can be prevented.

A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.

Structure and manufacturing method of semiconductor memory device

A semiconductor memory device () comprises a memory cell array () in which memory cells each have a variable resistance element and the memory cells in the same row are connected to a common word line and the memory cells in the same column are connected to a common bit line, wherein during a predetermined memory action, the voltage amplitude of the voltage pulse applied to an end of at least one of the selected word line and the selected bit line is adjusted based on the position of the selected memory cell in the memory cell array () so that the effective voltage amplitude of a voltage pulse applied to the variable resistance element of the selected memory cell to be programmed or erased falls within a certain range regardless of the position in the memory cell array ().

Semiconductor memory device

Provided are a nonvolatile variable resistor with a structure capable of suppressing an increase in resistance in a case where scaling is applied to reduce a projected area on a plane, a memory device using the nonvolatile variable resistor, and a scaling method of a nonvolatile variable resistor. A first electrode and a second electrode formed on a substrate face each other in a direction of a surface of the substrate. The first electrode is used as an inner electrode, a nonvolatile variable resistance body is formed on an outer surface of the first electrode and the second electrode is formed as an outer electrode on an outer surface of the nonvolatile variable resistance body.

Nonvolatile variable resistor, memory device, and scaling method of nonvolatile variable resistor

Input signals are weighted by weighting means composed of variable resistors, each made of an oxide thin film with a perovskite structure containing manganese, which changes resistance at room temperature according to the cumulative number of times a pulse voltage was applied and holds the resistance in a nonvolatile manner. Then, the weighted signals are inputted to an arithmetic unit. The oxide thin film used as each of the variable resistors changes its resistance, according to the cumulative number of times the input pulse was applied, and further holds the resistance in a nonvolatile manner even after the power supply is cut off. Thus, by changing the weighting factor according to the cumulative number of times the pulse voltage was applied, a neuro element more resembling a neuron of the human being is realized.

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Osaka, Japan

Masayuki Tajiri