Hitachi, Ltd.

Renesas Technology Corp.

Other

Hitachi Ulsi Systems Co., Ltd.

Hitachi Yonezawa Electronics Co., Ltd

Hitachi Global Storage Technologies Japan, Ltd.

Renesas Electronics Corporation

Hitachi Ulsi Engineering Corp.

Hitachi Microcomputer System, Ltd.

Meiji Dairies Corporation

Masayuki Suzuki

Hiromi Abe

Naotaka Hashimoto

Shinji Nishihara

Shinichi Fukada

Hiroshi Momiji

Masashi Sahara

Hiroyuki Uchiyama

Masanori Kojima

Shuji Ikeda

Shinichi Ishida

Hideo Miura

Toshihiko Shimizu

Yoshinori Takeuchi

Hidekazu Kohira

Masaaki Matsumoto

Hiromitsu Tokisue

Hidekazu Goto

Hideaki Tsugane

Yoshiaki Yoshiura

Sonoko Tohda

Noriyuki Takahashi

Yoshitaka Nakamura

Kazunari Suzuki

Masahiro Ichitani

Takafumi Nishita

Takashi Miwa

Kenichi Imura

Kouji Tsuchiya

Takao Matsuura

Takanori Hashizume

Satoru Yamada

Hideo Aoki

Isamu Asano

Takashi Nakajima

Tsuyoshi Tamaru

Yoshitaka Tadaki

Nobuyoshi Kobayashi

Toshihiro Sekiguchi

Takuya Fukuda

Keizo Kawakita

Masayoshi Saito

Kentaro Yamada

Naoki Fukuda

Masayoshi Hirasawa

Atushi Ogishima

Sonoko Abe

Hiromi Todorobaru

Hiroyuki Ohta

Tomio Iwasaki

Natsuki Yokoyama

Yoshio Homma

Yoshihiko Shimanuki

Teruhisa Ichise

Hidenori Suzuki

Seiichi Kondo

Ryo Haruta

Masayuki Uchida

Kiichiro Mukai

Hiromi Shimazu

Makoto Matsui

Munehiro Oda

Hiroshi Shinriki

Noriyoshi Goda

Masayuki Nakata

Naoki Kanda

Yoshinori Matsumuro

Fuminobu Maruyama

Tsuyoshi Baba

Hidekazu Tonouchi

The invention provides a peptide having an activity of inhibiting angiotensin-converting enzyme (ACE), and a food and drink and/or a pharmaceutical composition containing the peptide.

Peptide inhibiting angiotensin converting enzyme

A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

Method of fabricating semiconductor integrated circuit device

An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and' a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt suicide, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Method of fabricating semiconductor device

A non-leaded resin-sealed semiconductor device is manufactured by the steps of providing a conductive flat substrate (metal plate) of copper plate or the like, fixing semiconductor elements respectively to predetermined positions on the principal surface of the substrate by an insulating adhesive, electrically connecting electrodes on the surfaces of the semiconductor elements with predetermined partition parts of the substrate separate from the semiconductor elements by conductive wires, forming an insulating resin layer on the principal surface of the substrate to cover the semiconductor elements and wires, selectively removing the substrate from the rear of said substrate to form electrically independent partition parts whereof at least some are external electrode terminals, and selectively removing said resin layer to fragment the device into regions containing the semiconductor elements and the plural partition parts around the semiconductor elements. Thus, there is provided a compact non-leaded semiconductor device having a large number of electrode terminals.

Manufacturing method of a semiconductor device

A non-leaded resin-sealed semiconductor device is manufactured by the steps of providing a metal substrate having a front surface, a rear surface, a chip fixing partition part, partition parts arranged around the chip fixing partition part, and grooves defined between the partition parts; providing a semiconductor chip having a front surface, a rear surface, electrodes formed on the front surface; fixing the semiconductor chip on the chip fixing partition part of the front surface of the metal substrate; electrically connecting the electrodes of the semiconductor chip with the front surface of the partition parts of the metal substrate by conductive wires, respectively; and forming a resin body which seals the semiconductor chip, the conductive wires, and the front surface of the partition parts of the metal substrate. After the resin body forming step, the rear surface of the metal substrate is etched so as to electrically isolate the partition parts of the metal substrate from one another, and after the etching step, the etched surface of the metal substrateis plated with solder by print-plating method.

An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Method for fabricating semiconductor device

Method of fabricating semiconductor integrated circuit device with 99.99 wt% cobalt

A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and' a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

A magnetic disk unit includes a magnetic disk attached to a spindle so as to be rotatable, a slider having a magnetic head for reading/writing data onto/from the magnetic disk, a suspension for providing the slider with a predetermined load, and an actuator arm for positioning the slider attached to the suspension on the magnetic disk. A first pad including the magnetic head and second pads including no magnetic heads are disposed on an air bearing surface of the slider. During rotation of said magnetic disk, a part of the first pad keeps in contact with the magnetic disk. A load point of the suspension with respect to the slider is positioned between a leading edge of the slider and a position located at a distance equivalent to substantially 0.42 times a whole length of the slider from the leading edge of the slider.

Magnetic head gimbal assembly and magnetic disk unit

Growing community of inventors

Kokubunji, Japan

Masayuki Suzuki