Juniper Networks, Inc.

Nec Corporation

Idemitsu Kosan Company, Limited

Masayuki Shinohara

Shigeki Kato

Nobuyuki Kawabata

Hitoshi Hayano

Hideyoshi Nakamura

Takayuki Saeki

Masashi Yamanaka

Akira Yamamoto

Kiyohiko Nohara

Shuji Machida

Masato Kijima

Koki Hirano

Ruixue Fan

Tatsuya Housaki

Minoru Sugawara

Kyohei Miyajima

A method of carrying out arbitration in a packet exchanger including an input buffer temporarily storing a packet having arrived at an input port, and a packet switch which switches a packet between a specific input port and a specific output port, includes the steps of (a) concurrently carrying out a first plurality of sequences in each of the sequences basic processes for at least one of the input buffer and the output port are carried out in a predetermined order, and (b) making an allowance in each of the sequences for packets to be output through output through output ports at different times from one another.

Arbiter circuit and method of carrying out arbitration

A packet switching equipment and a switch control system employing the same performs operation of the switch core portion independent of content of decision of an arbiter portion and overall equipment can be constructed with simple control structure. The packet switching equipment includes input buffer portions temporarily storing packets arriving to the input ports and outputting packets with adding labels indicative of destination port numbers, a switch core portion for switching the packets on the basis of labels added to the input buffer portions, and an arbiter portion adjusting input buffer portions to provide output permissions for outputting to the output ports. A sorting network autonomously sorting and concentrating the packets on the basis of the labels added to the packets is employed in the switch core portion.

Packet switching equipment and switching control method

Arbitration is performed in a packet exchanger. In one implementation, a device for performing the arbitration may include input ports configured to each receive sequences that define a packet and output ports. A packet switch concurrently process multiple ones of the received sequences to select an output port for each of the received sequences, the packet switch transferring the received sequences to the selected output ports for output from the device at different times from one another.

A process for producing a polyolefin-based resin composition comprises, in the first polymerization stage, polymerizing an &#x3b1;-olefin having 4 to 20 carbon atoms, a styrene or a cyclic olefin in the presence of a specific catalyst and, in the second polymerization stage, copolymerizing the obtained polymer with an &#x3b1;-olefin having 2 to 20 carbon atoms, a styrene or a cyclic olefin in the presence of a polyene. A polypropylene composition has a branching parameter a and a branching index g in specific ranges. The curve showing the change in viscosity under elongation with time, the degradation parameter D or the content of a high molecular weight component is specified. The polyolefin-based resin composition exhibits excellent uniformity and improved workability in melting due to improved tension in melted condition. The polypropylene composition exhibits excellent melting elasticity and secondary workability and provides foamed molded articles, sheets and blow molded articles.

Process for producing polyolefin resin composition and polypropylene composition

A method of carrying out arbitration in a packet exchanger including an input buffer temporarily storing a packet having arrived at an input port, and a packet switch which switches a packet between a specific input port and a specific output port, includes the steps of (a) concurrently carrying out a first plurality of sequences in each of the sequences basic processes for at least one of the input buffer and the output port are carried out in a predetermined order, and (b) making an allowance in each of the sequences for packets to be output through output ports at different times from one another.

In candidate selection to select the queue issuing the connection request to a certain output port out of a plurality of logic queues provided in an input buffer section of an input buffer type ATM switching system to store cells for each output port and each connection, whether a logic queue holds cells in predetermined order is checked, and the logic queue located next to the queue to which gained the right to connect to an output port last time is taken as a start point of the rotation priority control to select the logic queue holding the cell searched first.

Switch control system in ATM switching system

To realize the traffic control for controlling congestion in an ATM switchboard and assuring the throughput of VCs using the same output port. A buffer occupancy value measuring section measures the queue length of each of the output port buffers and stores the data in a buffer occupancy value table. A back-pressure outputting section outputs a transmission restart signal when a queue length in the buffer occupancy table is equal to or less than a fist threshold, a transmission control signal when the queue length is between the first threshold and a second threshold, and a transmission stop signal when the queue length is equal to or more than the second threshold as back pressure signal respectively. A cell transmission control section transmits an ATM cell without comparing a transmission time with the present time when the instruction of a back pressure signal corresponding to a destination port indicates 'restart' and transmits an ATM cell only when the transmission time is earlier than the present time if the instruction indicates 'control'.

Switch control circuit and control method of ATM switchboard

A call reception control circuit 1 sets each guaranteed band width required for assuring communication quality of the respective band width demand classes in the corresponding N counter Nc, Ntv and Nv at a certain time interval Ts. The call reception control circuit 1 also sets values defined by the ratio of the W counter Wabr and Wubr of the respective best effort class to use the remained band width. The value 1 is subtracted from each value of the N counter Nc, Ntv and Nv and W counter Wabr and Wubr at every output of the cell from the corresponding class. A priority control process circuit 2 outputs cells to an output channel 3 according to priority levels giving a priority to the band width demand class having the value of the N counter not set to 0 over the band width demand class and the best effort classes having the value of the N counter set to 0.

Asynchronous transfer mode exchange system and priority control method

An asynchronous transfer mode switching system including a core switch section (CS102) in an output buffer-type configuration which has an ATM switching function between high-rate input and output ports, an input buffer module section (IXB20) which multiplexes plural low-rate input line to the high-rate input port of the core switch section, and an output buffer module section (OXB30) which separates the output of a high-rate output port of the CS into plural low-rate output lines. The IBX enables queuing for each output line and each service class. The OXB enables queuing for output line and service class accommodated by itself. When the buffer occupancy exceeds a threshold value, the OXB originates a cell inhibiting signal to the CS. When the queue length for each output port exceeds a threshold value, the CS originates the cell inhibiting signal to all IXBs. The IXB controls to stop a cell transmission according to the cell inhibiting signal. An execution throughput is increased by suppressing occurrence of congestion inside an ATM exchange. The evenness of throughput is guaranteed between virtual channels using the same output line.

ATM switching system which separates services classes and uses a code

In an ATM cell buffer managing system in an ATM node equipment, a buffer occupied amount of each individual logical channel of a buffer memory is measured by a buffer occupied amount counting portion, and a threshold value for each individual logical channel is dynamically derived on the basis of the measured buffer occupied amount for making judgement whether an input ATM cell can be received or not per each logical channel. By this, in the buffer memory, effective throughput of upper layer packet level can be improved.

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Tokyo, Japan

Masayuki Shinohara