Taiyo Yuden Co., Ltd.

Hitachi, Ltd.

Nec Corporation

Other

Kyocera Corporation

Masayuki Satou

Isao Shimizu

Hiroshi Fukiage

Koshi Sato

Hideaki Yoshida

Mitsunori Katsu

Hiroyuki Kozutsumi

Seiji Yoshikawa

Toshiki Hatori

A communication control device selects, based on scenario information, one or more of a plurality of reverse proxy devices that transfer information transmitted and received between an information processing device and a mounted device of a moving body. The communication control device performs operation control of the selected reverse proxy device. The communication control device selects the scenario information used for operation of the reverse proxy device based on an operation start signal transmitted from the mounted device, and transmits the scenario information to the mounted device.

Communication control device, communication control system, mounted device, communication control method, and program

This invention is directed to an encryption communication system for preventing leakage of a common key and improving the confidentiality of communication information. The encryption communication system uses a pair of a first private portion and a first public portion and a pair of a second private portion and a second public portion in a key predistribution system (KPS) The encryption communication system comprises a ciphertext generator that generates a ciphertext by generating, in a first security chip (TPM) of a first communication apparatus, a first common key by the first private portion held in the first security chip using the second public portion transmitted from a second communication apparatus as a communication partner, and encrypting a plaintext using the first common key in the first security chip, and a decryptor that generates a plaintext by generating, in a second security chip of the second communication apparatus, a second common key by the second private portion held in the second security chip using the first public portion transmitted from the first communication apparatus as a communication partner, and decrypting the ciphertext received from the first communication apparatus using the second common key in the second security chip.

Encryption communication system, encryption communication method, security chip, communication apparatus, and control method and control program of communication apparatus

Main memory access from a CPU is reduced, and thus an increase in speed of data processing is achieved. Provided is a reconfigurable device () connected to a main memory (). The reconfigurable device () includes a plurality of logic sections connected to each other by an address line or a data line. Each of the logic sections includes a plurality of address lines, a plurality of data lines, an address decoder that decodes addresses input from part of the plurality of address lines, and a memory cell array unit that includes a plurality of memory cells specified by decode lines of the address decoder, and outputs data read from the specified memory cells to the data lines. An address line of the memory cell array unit is connected to a data output line (RD) of the main memory.

Reconfigurable device

There is provided a logic device including memory cell units. Each of the memory cell units includes a pair of bit lines arranged corresponding to a column of memory cells, a word line, and an inverter unit connected to the pair of bit lines. The inverter unit includes a first CMOS and a second CMOS. The first CMOS is configured to receive an input signal from one of the pair of bit lines. The first CMOS includes a first MOS transistor and a second MOS transistor. The second CMOS is configured to receive an input signal from the other of the pair of bit lines. The second CMOS includes a third MOS transistor and a fourth MOS transistor. The inverter unit is configured to output a first differential signal and a second differential signal as a data signal.

Reconfigurable logic device configured as a logic element or a connection element

There is provided a reconfigurable semiconductor device including a plurality of logic units connected to each other using an address line or a data line, each logic unit including a plurality of address lines, a plurality of data lines, a clock signal line configured to receive a system clock signal, a delay element configured to delay the system clock signal, a memory cell unit configured to operate in synchronization with a clock signal, and an address decoder configured to decode an address signal to output the decoded signal to the memory cell unit. The logic unit configuring a combination logic circuit operates in synchronization with a delayed clock signal outputted from the delay element.

Reconfigurable semiconductor device

There is provided a reconfigurable semiconductor device including a plurality of circuit blocks each including a reconfigurable logic unit, and an analog circuit configured to convert an analog signal from the outside into a digital signal to output the digital signal to the reconfigurable logic unit, and convert a digital signal outputted from the reconfigurable logic unit into an analog signal to output the analog signal to the outside. The circuit block has a rectangular shape, is connected to the two adjacent circuit blocks from one side with a plurality of analog lines, and is connected to the other two adjacent circuit blocks from the other side on a side opposite to the one side with a plurality of analog lines.

A reconfigurable logic device includes logic units and allows logic circuits to be formed according to configuration data. The logic units each include a configuration memory that stores first and second configuration data, a first address input line through which a clock is inputted as a first address for the configuration memory, a second address input line through which an input of a data input line is inputted as a second address for the configuration memory, a register unit that, according to the clock, reads the second configuration data specified by the first address from the configuration memory and retains the second configuration data, and outputs the first configuration data in a previous state, and a multiplexer that, according to the first or second configuration data outputted from the register unit, selectively combines a data input from the data input line and a data output to a data output line.

Reconfigurable logic device

A semiconductor device capable of reconfiguration, including a plurality of logic units which are connected to each other by an address line or a data line, wherein each of the logic units includes: a plurality of address lines; a plurality of data lines; a clock signal line to receive a system clock signal; a first and a second memory cell units which operate synchronously with the clock signal; a first address decoder which decodes an address signal and outputs a decode signal to the first memory cell unit; a second address decoder which decodes an address signal and outputs a decode signal to the second memory cell unit; and an address transition detection unit which generates an internal clock signal and outputs the internal clock signal to the first memory cell unit, when a transition of the address signal input from the plurality of address lines is detected, wherein the first memory cell unit operates synchronously with the internal clock signal, and the second memory cell unit operates synchronously with the system clock signal.

Semiconductor device

A semiconductor device capable of reconfiguration, including: a plurality of logic units which configure an array and are connected to each other, wherein each logic unit includes a pair of a first and a second memory cell units, each of the first and the second memory cell units operates as a logic element when truth value table data is written in, which is configured so that a logic calculation of an input value specified by a plurality of addresses is output to a data line, and/or operates as a connection element when truth value table data is written in, which is configured so that an input value specified by a certain address is output to a data line to be connected to an address of another memory cell unit, a latter stage of the first memory cell unit includes a sequential circuit which synchronizes with a clock, and the logic units include, for each pair of the first and the second memory cell units, a selection unit which selectively outputs an address to the first or the second memory cell unit in accordance with an operation switch signal.

An arrangement and wiring method of a reconfigurable semiconductor device, including: generating a net list based on a circuit description in which a circuit configuration is described; extracting a sequential circuit data set which is to be scanned from the net list; generating a first truth value table data set so as to write into a first set among plurality of memory cell units from the sequential circuit data set which is to be scanned; and generating a second truth value table data set so as to write into a second set among the plurality of memory cell units from a combination logic circuit data set of the net list.

Method for arranging and wiring reconfigurable semiconductor device, program therefor, and arranging and wiring apparatus

A test circuit comprised of a microprogram controlled control unit for generating a test pattern (addresses and data) for each memory in accordance with a predetermined algorithm and reading written data, an arithmetic unit, and data determining means for determinating the read data and outputting the result of determination is provided over a semiconductor chip equipped with a memory.

Semiconductor integrated circuit and method of checking memory

A test circuit comprised of a microprogram controlled control unit for generating a test pattern (addresses and data) for each memory in accordance with a predetermined algorithm and reading written data, an arithmetic unit, and data determining means for determining the read data and outputting the result of determination is provided over a semiconductor chip equipped with a memory

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Tokyo, Japan

Masayuki Satou