Fujitsu Corporation

Masayuki Okamoto

Kenji Yoshida

Daisuke Miura

Shuji Yoshida

Toshio Arakawa

Mitsuaki Nagasaka

Hiroyuki Honda

Mitsuru Yamauchi

Toshiya Mima

In a layout method for an LSI having a plurality of cells, automated arrangement of cells is performed on the basis of a netlist, which has cells and connection data therefor, and timing conditions, and, once a timing optimization processing is performed so that a plurality of cells are arranged on a chip, global wiring processing is implemented and the wiring congestion rate is analyzed. In addition, in small regions where a wiring congestion rate is so high that detailed wiring processing is judged to be difficult, cell rearrangement processing is implemented. Next, detailed wiring processing is performed with respect to the cells which have been rearranged. The rearrangement of cells is performed only in small regions with a high congestion rate, with the result that the overall cell arrangement in which timing is optimized is not changed markedly, whereby it is possible to reduce the probability of wiring being impossible in the course of the detailed wiring processing.

LSI layout method and apparatus for cell arrangement in which timing is prioritized

Each binary carry logic circuit of half adder circuits other than that for the least significant digit comprises a transfer gate turned on when an input bit A is active and receiving a carry-in bit *C at its data input, and a transistor , turned on when the input bit A is inactive, connected between a power supply potential VDD and the data output of the transfer gate a signal on which is a carry-out bit *C . Transfer gates to of binary carry logic circuits other than that for the least significant digit are connected in chain, and are simultaneously on/off controlled by input bits A to A , letting the carry-in bit *C from the least significant digit propagate through the transfer gate chain at a high speed.

Logic circuit for fast carry/borrow

Disclosed is a method for automatic wiring design between block circuits of an integrated circuit, which performs an automatic connection between an inter-block wire disposed between a first circuit block and a second circuit block, and terminals formed along sides of the first and second blocks, the sides facing each other. The method comprises the steps of (S ) sorting the terminals according to the width thereof; and (S S ) selecting a terminal from the terminals in descending order of the width, and connecting between the selected terminal and an inter-block wire belonging to a same net as the terminal. In another embodiment, the method comprises the steps of (a) sorting the terminals, connected to a power supply wire, according to the value of electric current passing through the terminals; and (b) selecting a terminal from the terminals in descending order of the value of electric current and connecting between the selected terminal and an inter-block wire belonging to a same net as the selected terminal.

Method and apparatus for automatic wiring design between block circuits of integrated circuit

In a system for reproducing an image pattern data, a decision point designation means exclusively designates a decision point at the corresponding coordinate position in a coordinate region of image pattern reproduction in divisional coordinate regions when a decision point extracted based on a region decision data obtained by region decision means is located in a region of the first kind, exclusively designates a decision point at the scan starting point of a coordinate region of image pattern reproduction when the extracted decision point is located in a region of the second kind, designates no decision point when the extracted decision point is located in a region of the third kind, and, based on the designation by the decision point designation means, a shading of dots of the image is carried out.

Reproduction of image pattern data

A computer graphic apparatus uses a method and apparatus to approximate a polygonal line of a plurality of line segments (L.sub.1, L.sub.2 . . . ) to a curve (X). The curve is divided into two curve portions (P.sub.10 P.sub.11, P.sub.11 P.sub.02) at a division point (P.sub.11). An error (e) between a line segment (P.sub.01 P.sub.02) linking the start and end points (P.sub.01, P.sub.02) of the curve and the division point is compared with a predetermined value (V.sub.th). When the error is small, the line segment is treated as one part of the polygonal line, but in another case, the above-mentioned process is repeated.

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Kawasaki, Japan

Masayuki Okamoto