Fujitsu Corporation

Masayuki Naganuma

Tetsu Tanizawa

Yoshiyuki Suehiro

A method of placing and routing elements of a semiconductor integrated circuit picks out a signal net, a driver of the signal net, and load cells driven by the driver among the elements of the integrated circuit, places the driver at a first position, defines a first range based on the first position, determines a second position in the first range, defines a second range based on the second position, and collectively places the load cells of a predetermined number in the second range. Namely, the method deals with a signal net in the integrated circuit, a driver of the net, and load cells driven by the driver. The method sets conditions on the signal net, driver, and load cells, when placing and routing the elements of the integrated circuit, to thereby reduce skew (skew time), wiring overhead, and time delay in the integrated circuit and speedily and easily place and route the elements.

Method of and apparatus for placing and routing elements of

A CMOS output buffer circuit is reduced its output pulse noise and excess current which runs through the CMOS when it is switched ON and OFF. In the gate circuits of p and n channel FETs of the CMOS output buffer circuit, a time constant circuit is inserted. The time constant circuit slightly slows down the voltage variation of input signals to the gates, so the rush current which runs through the output FETs for charging up or discharging the load capacitance is decreased. So, the dI/dt noise is reduced, but the total switching time of the output circuit is not so much affected. By the difference of time lags between the build up and trailing edges of input pulses for both output FETs, one of the output FETs becomes conductive always after the other one is cut off. So, the excess current is reduced. The time constant circuit is composed of a series connected resistor and inverter circuit, connected between positive and negative voltage sources. The time constant circuit many be provided in both or one of the driving circuits for the output FETs. The resistors may be replaced by FETs having proper internal resistances.

High power buffer circuit with low noise

A master slice type integrated circuit for providing various circuits by altering the routing of interconnections comprises a plurality of input/output cells arranged in a peripheral region on a semiconductor chip, the input/output cells each comprising pads for connection with an external circuit, input wiring regions each for accommodating input interconnecting lines transmitting input signals applied to the pads, and output circuit regions each for forming output buffers; and a plurality of basic cells being arranged in a region on the chip surrounded by the arrangement of the input/output cells. Two adjacent input/output cells are paired with each other. The output circuit regions of the pair of the input/output cells are arranged in the vicinity of a boundary of the pair. The input wiring regions of the pair are arranged in the vicinity of boundaries with respect to other pairs.

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Kawasaki, Japan

Masayuki Naganuma