Hitachi, Ltd.

Masayuki Miyoshi

Takayuki Nakagawa

Shigeo Nagashima

Koichiro Omoda

Yoshio Takamine

Yoshiharu Kazama

Shunsuke Miyamoto

Yoshiaki Kinoshita

Yukio Ikariya

Masato Morita

Yoshinori Sakataya

A computer implemented logic simulation method, for inspecting logical operations of large scale logic circuits, computes a variation of an output of at least one latch in a clock synchronized logic circuit. The clock-synchronized logic circuit contains a combination logic circuit and a plurality of logic gates. Each of the logic gates have at least one input signal and several other inputs connected to clocking signal sources of different phases. The latch is activated by the rise or fall of the clock signals for holding the output from the combination logic circuit. The method thus implements sampling instants of the output for ascertaining the logical operations of the large scale circuits.

Circuit simulation method with clock event suppression for debugging LSI

In automatic development of the higher hierarchic logic into the lower hierarchic logic in a hierarchic logic designing, identification codes are beforehand assigned to logic components of the higher hierarchic logic, and the identification codes are also assigned to the lower hierarchic logic data when developing the higher hierarchic logic into the lower hierarchic logic in order to establish correspondences between the higher and lower hierarchic logic, thereby allowing a higher-speed logic compare operation with respect to a design change on the higher or lower hierarchic logic and enabling the automatic update of the lower hierarchic logic by use of the higher hierarchic logic as the master.

Method for generating logic circuit data

A logic simulation is executed using a real circuit as a part of a simulation model of a logic circuit subjected to the logic simulation. The simulation model is formed of the real circuit and a simulation circuit, and the operation of the real circuit and the logic simulation of the simulation circuit are performed alternately. The operation of the real circuit is performed in response to an input signal thereto representing the condition of the output node of the simulation circuit, while the logic simulation of the simulation circuit is executed in response to a stimulus in the form of an output signal of the real circuit which is applied to the input node of the simulation circuit.

Method of digital logic simulation

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Hadano, Japan

Masayuki Miyoshi