Hitachi, Ltd.

Dai Nippon Insatsu Kabushiki Kaisha

Elpida Memory, Inc.

Mitsubishi Denki Kabushiki Kaisha

Hitachi Device Engineering Co., Ltd.

Dai Nippon Printing Co., Ltd.

Texas Instruments Corporation

Adv Antest Corporation

Mitsui Toatsu Chemicals, Incorporated

Kawasaki Steel Corporation

Kao Corporation

Dexerials Corporation

Yoshino Kogyosho Co., Ltd.

Ps4 Luxco S.a.r.l.

Hitachi Ulsi Systems Co., Ltd.

Masayuki M Nakamura

Jumpei J Kanto

Hiroshi H Eguchi

Hitoshi Saito

Goro Kitsukawa

Tsugio Takahashi

Koumei Kafuku

Takesada Akiba

Yasushi Kawase

Komei Kafuku

Kazuhiko Kajigaya

Hiroki Fujisawa

Kazuyoshi Oshima

Kazuyuki Miyazawa

Hidetoshi Iwai

Keiji Sodeno

Seiji Kodama

Hitoshi Tanaka

Riichiro Takemura

Takayuki Kawahara

Tomonori Sekiguchi

Hugh Pryor McAdams

Satoru Akiyama

Masanori Akada

Chiaki Dono

Keisuke Takuma

Tetsuro Matsumoto

Ryohei Takiguchi

Toshikazu Tachibana

Tsukasa Ohyama

Hitoshi Koshida

Yoriaki Matsuzaki

Isamu Ghoda

Hiroaki Nakaya

Yasushi Shimokawa

Paulette Thurston

Junji Chiba

Kaoru Suda

Susumu Mizugami

Mamoru Tabuchi

Naotake Ritoh

Masakazu Aoki

Takayuki Abe

Yoshinobu Nakagome

Katsuyuki Oshima

Chikara Kondo

Kunio Uchiyama

Yasuji Koshikawa

Hiromasa Noda

Toshio Sugano

Seiji Narui

Atsushi Hiraishi

Shinichi Miyatake

Yasushi Sato

Kanji Oishi

Masaki M Kutsukake

Makoto Hanawa

Tatsuya Kita

Jeffrey E Koelling

Makoto Morino

Jitsuhiko Ando

Hideyuki Yoko

Hiroshi Otori

Masato Hasegawa

Shunichi Saito

Fumiyuki Osanai

Hidesato Kizaki

Tetsuya Kobayashi

Nobuhisa Nishitani

Kazuhiro Kimura

Toshihiko Baba

Toshiyuki Kobayashi

Shinichi Inaba

Ryu Shimada

Takanori Fujita

Junji Miyata

Takeshi Omi

Katsuhiro Kamakari

Nobuyoshi Nakatani

Fujiya Ikuta

Kazuo Katou

Kouichi Ishii

Taketomo Matuzaki

Masaru Takeshita

Provided is a water-purifying agent that is excellent in water purifying performance, can be suitably used in an automated wastewater purification apparatus, and is formed of a granulated product including a mixture of a powder ofand a polymeric flocculant, wherein a median diameter of the granulated product is 250 micrometers or greater but 850 micrometers or less.

Water cleaning agent and water cleaning method

A semiconductor storage device is provided with a memory cell array comprising a plurality of word lines including word lines that are adjacent to one another; and a TRR address conversion unit that selects the word line in response to the input of an address signal indicating a first value while in a first operation mode and selects the word line in response to the input of an address signal indicating a first value while in a target row refresh mode. Due to the fact that address conversion is performed on the semiconductor storage device side in the present invention, it is sufficient for a control device to output, for example, the address of a word line having a high access count to the semiconductor storage device during a target row refresh operation. As a result, control of the target row refresh operation on the control device side is facilitated.

Semiconductor storage device and system provided with same

A trigger-type liquid sprayer of the present invention is provided with a liquid sprayer bodyhaving a nozzleand a trigger leverand a shroudcovering the liquid sprayer bodyand sprays a liquid from a spray holein the nozzleby a pulling operation of the trigger lever. The nozzleis rotatable with respect to the liquid sprayer bodyand provided so as to open/close a flow passage for the liquid according to a rotational position of the nozzlewhen an operation levermounted on the nozzleis rotationally moved, and an abutment portionfor positioning the nozzleat a position where the flow passage is opened through abutment of the operation leveris provided at the shroud

Trigger-type liquid sprayer

A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.

Load reduced memory module and memory system including the same

There are provided a duty ratio control apparatus for altering a duty ratio of a clock signal to output an altered clock signal, including a first variable delay section that outputs a first delayed clock signal generated by delaying the clock signal by a predetermined first delay time, and a phase comparing section that compares, in terms of phase, an edge of the clock signal and an edge of the first delayed clock signal and generates the altered clock signal having a pulse width determined by a phase difference obtained by the comparison, and a duty ratio control method.

Duty ratio control apparatus and duty ratio control method

A ZQ calibration command is internally generated from an external command different from a ZQ calibration command so as to automatically perform an additional ZQ calibration operation. A command interval between an inputted command and a next command is effectively employed to obtain a ZQ calibration period. The external command different from the ZQ calibration command is preferably a self-refreshed command. The addition of the ZQ calibration operation shortens intervals between ZQ calibration operations. Thus, it is possible to obtain a ZQ calibration circuit capable of performing a ZQ calibration operation more accurately.

ZQ calibration circuit and a semiconductor device including a ZQ calibration circuit

A semiconductor device is configured to prevent misprogramming of fuse circuits therein. The semiconductor device includes the following elements. A group of fuse element circuitsis configured to store a first data defining the circuit configuration. A fuse element circuitis configured to store a second data representing inhibition of programming the group of fuse element circuits. A control logic circuitis configured to program the first and the second data on the fuse element circuits. An AND gate circuitis configured to inhibit the control logic circuitfrom programming the group of fuse element circuitson condition that the fuse element circuithas been programmed.

Semiconductor device

There is provided an oscillator including: a reference signal generator that generates a reference signal having a reference frequency; a phase comparator that outputs a voltage in accordance with a phase difference between the reference signal and a feedback signal; a loop filter that receives a voltage output from the phase comparator, and gain-adjusts a voltage output from the phase comparator by means of an external control signal; a voltage controlled oscillator that oscillates an output signal at a frequency in accordance with an adjusted signal having been gain-adjusted by the loop filter; and a frequency divider that feeds back a frequency-divided signal resulting from frequency-dividing the output signal, to the phase comparator as the feedback signal.

Oscillator and a tuning method of a loop bandwidth of a phase-locked-loop

A reference voltage generating circuit includes a current generating section, a voltage generating section, a voltage dividing circuit, and a synthesis section. The current generating section generates a first current having a positive temperature coefficient. The voltage generating section generates a voltage having a negative temperature coefficient. The voltage dividing circuit divides the voltage of the negative temperature coefficient, generated by the voltage generating section. The synthesis section generates a voltage which is the sum of a terminal voltage obtained on causing the first current through a resistor and a voltage obtained on dividing the voltage having the negative temperature coefficient by the voltage dividing circuit, and outputs the sum voltage generated as a reference voltage.

Reference voltage generating circuit

The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which is controlled to be a difference between access time determined by an external clock and the latency and column cycle time. These delay circuit blocks are controlled so that the delay of each delay circuit is a suitable value in accordance with column latency and an operating frequency, and each delay is controlled corresponding to dispersion in a process and operating voltage and a change of operating temperature.

Semiconductor memory device

In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS transistor gate voltage control circuit connecting a sense amplifier and a memory cell array, a shared MOS transistor gate voltage (SHR) is lowered in two stages and bit line capacitance to be amplified is reduced taking noise during the sensing into consideration so that the sense speed is increased. Therefore, a timing of activating a column selection signal can be hastened and as a result, data read time can be reduced.

A reference voltage generating circuit is described. The circuit includes a current generating section that generates a first current having a positive temperature coefficient, a voltage generating section that generates a voltage having a negative temperature coefficient, a synthesis section that generates a voltage which is the sum of a voltage having a positive temperature coefficient and developed across both terminals of a resistor, where the voltage has a negative temperature coefficient, and a compensation current generating section that generates a second current having a positive temperature coefficient. The current corresponding to the sum of said first and second currents is caused to flow through the resistor. The synthesis section generates a voltage which is a sum of a terminal voltage of the resistor by the sum current of the first and second currents and the voltage having a negative temperature coefficient.

A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and columns selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.

Semiconductor memory

A semiconductor integrated circuit device includes a memory array having first to Nth banks, where N is an integer greater than or equal to 2. The memory array further includes a redundancy block having first to Nth column recovery circuit blocks corresponding to the first to Nth banks, first to Nth row recovery circuit blocks corresponding to the first to Nth banks, first to Nth ECC fuse blocks corresponding to the first to Nth banks, and first to Nth ECC circuits corresponding to the first to Nth banks. During initial cycles, the first to Nth ECC circuits correct errors in column recovery fuse data in the first to Nth column recovery circuit blocks and errors in row recovery fuse data in the first to Nth row recovery circuit blocks by using ECC fuse data in the first to Nth ECC fuse blocks, respectively.

Redundancy semiconductor memory device with error correction code (ECC) circuits for correcting errors in recovery fuse data

A semiconductor IC device includes, in a substrate, a P-type well region having a dynamic memory array section and applied with a reduced back bias voltage suitable for refreshing. Also included is a P-well region where N-channel MOSFETs of a peripheral circuit are formed. This P-well region is applied with a back bias voltage of an absolute value smaller than that applied to the P-type well of the memory array section. A P-type well section, where there are formed N-channel MOSFETs of an input circuit or an output circuit connected with external terminals, is applied with a back bias voltage of an absolute value large enough to provide a measure of protection against undershoot, while the refresh characteristics are improved by reducing the leakage current between the source/drain region connected with a capacitor and the P-type well, to thereby raise the operation speed of the peripheral circuit.

Semiconductor integrated circuit device

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Tokyo, Japan

Masayuki M Nakamura