Hitachi, Ltd.

Hitachi Techno Engineering Co., Ltd.

Masayuki Kyooi

Hideyasu Murooka

Naoya Kitamura

Takashi Inoue

Hitoshi Yokono

Hitoshi Oka

Fusaji Shoji

Fumio Kataoka

Hideo Arima

Haruhiko Matsuyama

Osamu Yamada

Hidetaka Shigi

Tetsuya Yamazaki

Masashi Nishiki

Yukio Maeda

Takehiko Hasebe

Akimi Miyashita

Mutsumasa Fujii

Kiyonori Kogawa

Nobuaki Ooki

Masami Kawaguchi

Noriaki Ujiie

Keiichiro Torii

Minoru Kubosawa

A multi-layer wiring substrate capable of high density packaging, and a method of manufacturing the same, in which a carrier substrate, in which through holes can be easily formed in high density corresponding substantially to a pitch of connecting terminals in a semiconductor chip, and build-up layers are formed on the substrate with the application of a conventional build-up technique. When the build-up technique for repeatedly forming insulating layers and wiring layers on a carrier substrate is used to manufacture a multi-layer wiring substrate, the carrier substrate is formed in the following manner. First, an insulating resin layer is formed in a copper foil, in which a plurality of first windows are regularly provided, to cover the copper foil, and the resin layer fills the interior of the windows. Subsequently, second windows of a particular shape are provided in regions of layers of the insulating resin filled in the windows, and independent conducting paths are formed through the second windows to extend from front sides of the second windows to back sides thereof. The conducting paths are formed radially to be spaced a substantially equal distance from centers of the respective second windows.

Multi-layer wiring substrate and manufacturing method thereof

A process for the fabrication of an interconnected multilayer board involves the steps of forming a metallic under-conductive layer on a base substrate, forming a windowed resist layer on the metallic under-conductive layer, filling windows of the resist layer with a conductor by plating thereby forming a conductor layer, forming another windowed resist layer on the conductor layer and filling windows of this resist layer with a conductor by plating, thereby forming a via-hole layer and to provide a two-level structure of the conductor layer and the via-hole layer. Thereafter, the resist layers and portions of the metallic under-conductor layer other than those in contact with a lower face of the conductor constituting the conductor layer are dissolved to form a two-level skeleton structure of conductor lines and spaces within the skeleton structure are filled with a varnish in a solventless form and the varnish is cured.

Process for fabricating an interconnected multilayer board

Described herein are interconnected mutilayer boards and their fabrication processes. Multilayer conductor lines of a skeleton structure are formed by conducting multilayer metallization while including all resist layers and metallic under-conductive layers and then removing the resist layers and metallic under-conductive layers at once. Spaces between the multilayer conductor lines of the skeleton structure are then filled with a solventless varnish so that insulating layers are formed. Modules making use of such interconnected multilayer boards and computers having such modules are also described.

Interconnected multilayer boards and fabrication processes thereof

A hot press including a displaceable sleeve for surrounding materials of a multi-layer substrate under a reduced pressure condition, a gas pressurizing condition and a heating condition with thermal plates. Upper and lower sealing units seal an interior of the sleeve, with a mechanism lowering and raising the sleeve. A pilot check mechanism prevents a lower bolster from raising/lowering upon the reduced pressure condition and the gas pressure condition, and a retainer maintains the lowered or raised condition of the sleeve. The multi-layer substrate is formed under the reduced pressure condition and the gas pressure condition. Accordingly, the atmosphere and moisture between the materials of the multi-layer substrate and volatile composition are removed. Additionally, a void generated during the heat and pressure process by the heating plates is eliminated from the multi-layer substrate. By carrying out the formation of the multi-layer substrate at the heat and pressure by the heating plates under the gas pressure condition, a final dimensional precision and shape are enhanced and a warpage or twist is suppressed.

Hot press

A method and an apparatus of forming a multilayer printed circuit board which can positively remove voids in the prepregs in the printed board and enhance the reliability of the produced printed circuit board and is superior in economy, wherein a laminated assembly of a plurality of printed circuit board components and a plurality of prepregs alternately laminated on each other is sandwiched between upper and lower jig plates, and the laminated assembly sandwiched between the jig plates is clamped between heating plates of a bonding press to heat the assembly to a predetermined temperature, and, thereafter, a pressure is applied to the upper and lower jig plates so as to urge them against each other for bonding the printed circuit board component and the prepregs. An exterior pressurizing means is provided around the printed circuit board components and the prepregs sandwiched between the upper and lower jig plates in order to prevent the molten prepregs from flowing outwardly, thereby raising the fluid pressure of the molten prepregs to squeeze out air bubbles existing in the prepregs.

Method of forming a multilayer printed circuit board and apparatus

Growing community of inventors

Yokohama, Japan

Masayuki Kyooi