Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Renesas Technology Corp.

Mitsubishi Denki Kabushiki Kiasha

Masayuki Koyama

Michiru Hori

Makoto Hatakenaka

Hideo Nagano

Motoki Higashida

Naohiro Kobayashi

Tomoko Ando

Kikuo Muramatsu

Takahiko Arakawa

In a reception apparatus, a matched filter that has conventionally been arranged in a searcher unit is mounted on an acquisition unit together with a large scale memory. The large scale memory once stores reception chip signals, and thereafter outputs them to the matched filter and to the delay profile calculation unit. A setting register receives an acquisition signal and outputs it to the matched filter. The matched filter performs acquisition of the reception chip signals outputted from the large scale memory, and outputs a despread timing signal to a despread circuit, a code generation circuit and the delay profile calculation unit.

Reception apparatus using spread spectrum communication scheme

An information device packaged in one package includes a main function unit and an interface function unit. The main function unit includes a main processing circuit for executing signal processing related to a main function in the information device and a first microcomputer for controlling the main processing circuit by executing a first firmware program. The interface function unit includes an interface function unit including a first interface circuit for receiving data from an exterior device located outside of the information device to provide to the main function unit, a second interface circuit for performing an authentication operation with the exterior device, a second microcomputer for controlling the first interface circuit, and a memory for storing a second firmware program for controlling the first interface circuit.

Information device including main processing circuit, interface circuit, and microcomputer

An information device includes a main processing circuit for executing signal processing related to a main function in the information device, a main microcomputer for controlling the main processing circuit, a receiver circuit for interfacing with the outside of the information device, and an interface microcomputer for controlling the receiver circuit, the interface microcomputer being provided separately from the main microcomputer.

An adaptive filter includes: a plurality of delay circuits which receive a first signal, a second signal obtained by delaying the first signal, and a tap coefficient, and generates a first delay signal obtained by delaying the first signal, and a second delay signal obtained by delaying the second signal, and based upon the first delay signal and the tap coefficient, calculates a set point signal for each of the delay circuits; an addition circuit which adds the set point signals for a set point signal as a whole; and a coefficient calculation circuit which is placed in each of the delay circuits and which sequentially selects the second delay signals, and based upon the selected second delay signal and the set point signal as a whole, sequentially calculates the tap coefficients for the respective delay circuits.

Adaptive filter having a small circuit scale with a low power consumption and tap-coefficients updating method of adaptive filter

FIFO type memory is provided on a small circuit scale. Reading of data Dout<3:0> from a two-port type RAM (101) is executed with respect to the address specified by a read address ( ) in synchronization with the fall of a clock (CLK) provided to a clock end (CLR). Writing of data Din<3:0> on the RAM ( ) is executed with respect to the address specified by a write address ( ) in synchronization with the rise of a clock (CLK) provided to a clock end (CLW). In an address delayer ( ) after a read address ( ) taking an address value is outputted, a write address ( ) taking the same address value is always outputted with a fixed delay, so that a memory ( ) performs the FIFO type data input/output as a whole.

FIFO memory having reduced scale

In an error correction device, a chain search operation unit supplies a symbol string which has undergone error correction to a first FILO unit and supplies a symbol string which has not undergone error correction to a second FILO unit. A recovery process unit couples the first FILO unit with a de-randomizer if the error correction is normally performed and couples the second FILO unit with the de-randomizer if the error correction is not normally performed. The bit error rate is accordingly reduced compared with that of conventional devices which supply a symbol string subjected to error correction to a de-randomizer whether or not the error correction is normally made.

Error correction device for correcting error in input symbol string

A code synchronization decision circuit of Viterbi decoder including a trigger signal generator that produces a trigger signal every time a symbol counter counts a predetermined number of symbols defined externally. A second comparator compares, in response to the trigger signal, the number of errors of symbols counted by an error counter with a threshold value that is externally set, and supplies a masking signal generator with a synchronization signal or a slip signal in response of the compared result. The masking signal generator, in response to the signals, generates a masking signal for suspending the operation of the error counter and symbol counter for a time period, during which unsuitable codes will be supplied to the code synchronization decision circuit from a re-encoder of the Viterbi decoder as one of compared values for detecting symbol errors. This makes it possible for a user to set the threshold value and the number of symbols to be counted with ease, and to implement a code synchronization decision circuit of a Viterbi decoder capable of saving power.

Code synchronization decision circuit of Viterbi decoder

In a viterbi decoding apparatus, a depuncture circuit is always synchronized with the input of a correct convolutional code irrespective of the degree of noise in the transmission path of the convolutional code. A comparator (4) makes a comparison of error numbers of slip states 1 through N stored in registers (R1) through (RN) of the register group (2), respectively, to detect a register (Rk) (k=either of 1 through N) storing the minimum error number thereby to output a minimum slip state (MINSLIP) indicating the slip state k to a slip state determination portion (5). The slip state determination portion (5) determines the minimum slip state (MINSLIP) to be a determined slip state (DSLIP) when the minimum slip state (MINSLIP) continuously indicates the same slip state M times.

Viterbi decoding apparatus, method for controlling slip state of

It is possible to continuously obtain the function of FILO for plural sets of data while reducing regions for storing the data. A string of data input from a memory M0 is shifted to a memory M3, and is switched back and read from the memory M0. Consequently, the function of FILO can be obtained for the same string. On the other hand, a string of data input from the memory M3 is shifted to the memory M0, and is switched back and read from the memory M3. Consequently, the function of FILO can also be obtained for the same string. With these two data strings keeping a push-pull relationship each other, the data are shifted among the memories M0 to M3. Therefore, the number of elements of each data string is enough for that of required memories.

Bidirectional transfer type storage and method for controlling input and

From an input data signal (Data.sub.-- In) formed of a data signal complied with the MPEG standard including unit packets each formed of a sequence of 204 pieces of 8-bit-long unit data assigned in a sequence of 6-bit-long unit data, the original packet-unit data signal is reconfigured. Data having a length of 8 bits are sequentially extracted from two 6-bit-long unit data successively held in buffers (BS1, BS2). Correctness of the position of the head word of the packet is verified on the basis of whether a synchronizing code (Cd) indicating the head word repeatedly appears in the cycles of packets. It is determined whether a cycle of a packet has passed on the basis of a value counted in synchronization with an extraction signal (Dout), eliminating the necessity for the FIFO required in conventional devices. As a result, size reduction and cost reduction of the device are implemented.

Synchronizing device with head word position verification

A bidirectional FILO capable of continuously performing the function of the FILO for different groups of codes is used to reduce a circuit scale of a Reed-Solomon error correcting device. Coefficients of an error-locator polynomial .delta.(x) and an error-evaluator polynomial .omega.(x) obtained by using a Euclid method are obtained in order from a final digit of a code to a first digit thereof. Correspondingly, a corrector starts a Chien search in order from a final byte of the code to a first byte thereof. In response to the order of the search, each group of data RSIN (Reed-Solomon Input) having digit order reversed in a bidirectional FILO are given to the corrector. The code corrected by the corrector also has digit order reversed. Therefore, the digit order is returned to original order in the bidirectional FILO for returning digit order to original order, so that a code RSOUT (Reed-Solomon Input) is output. The bidirectional FILOs can be implemented by operation of a shift register type, for example.

Error correcting device

The configuration of a first-in first-out semiconductor storage device is simplified. A write address generating combinational circuit portion (100A) including no sequential circuits generates write addresses by using read addresses generated by a read counter portion (7).

FIFO memory device having address detection portion

A logic description conversion apparatus and a logic description conversion method are obtained according to which logic descriptions which include a long-term operation logic part which operates at an operation clock which is longer than a reference operation clock are converted into more advanced logic descriptions from which a logic circuit is accurately created. A source code which is formed by logic descriptions which includes a multi-clock transfer path (long-term operation logic part), is generated to a reference table which includes information about input control logic of an extracted register. Based on an indicator in which register name information of a receiving side of the multi-clock transfer path is registered and the reference table, the source code is converted into a source code which is formed by logic descriptions in which the long-term operation logic part and the input control logic are logically separated from each other. Since the long-term operation logic part and the input control logic are logically separated from each other, a logic circuit is accurately created by logic synthesis.

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Hyogo, Japan

Masayuki Koyama