Hitachi, Ltd.

Other

Tokyo Electron Limited

Hitachi Plant Engineering Construction Co., Ltd.

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Tokyo Electron Yamanashi Limited

Elpida Memory, Inc.

Hitachi Ulsi Engineering Corp.

Masayuki Kojima

Kazuo Nojiri

Shuji Ikeda

Atsushi Ogishima

Kazuyuki Suko

Yasuko Yoshida

Takafumi Tokunaga

Yoshiaki Sato

Tokuo Kure

Tetsuo Ono

Hironobu Kawahara

Kozo Watanabe

Takashi Yamada

Tatsumi Mizutani

Ryooji Fukuyama

Yoshimi Torii

Michimasa Hunabashi

Keizo Kuroiwa

Yoshinao Kawasaki

Motohiko Yoshigai

Koichiro Ishibashi

Hiroyuki Uchiyama

Norio Suzuki

Yasushi Goto

Norio Ishitsuka

Takashi Sato

Atsuyoshi Koike

Yasuo Kiguchi

Kenichi Kuroda

Masahiro Moniwa

Kiyonori Ohyu

Keiji Okamoto

Syunichi Hashimoto

Nozomu Matsuda

Kenichi Osada

Yutaka Kobayashi

Hideyuki Kazumi

Kunio Uchiyama

Ken Yoshioka

Masaru Izawa

Yoshitaka Tadaki

Yasuhisa Shimazaki

Hisashi Nakamura

Toshihiro Sekiguchi

Naoyuki Kofuji

Hiromichi Enami

Jun Murata

Norio Nakagawa

Osamu Kasahara

Hiroyuki Miyazawa

Akira Takamatsu

Hiroko Kaneko

Shinichi Horibe

Michimasa Funabashi

Toshio Maeda

Fumiyuki Kanai

Masaki Nagao

Hiroyuki Ichizoe

Maki Shimoda

Tadashi Umezawa

Kazuya Kadota

Hideo Miura

Eiichi Nishimura

Toshiaki Yamanaka

Satoshi Meguro

Naotaka Hashimoto

Katsuhiko Hotta

Takuya Fukuda

Hirofumi Yamamoto

Kota Funayama

Sadayuki Morita

Masayoshi Saito

Kazuhiko Noto

Hiroyuki Maruyama

Shigeki Tozawa

Masayoshi Hirasawa

Kyoichiro Asayama

Naomichi Mori

Shunichi Iimuro

Toshiro Aoto

Yoshikazu Ito

Masashi Arasawa

Akira Koshiishi

Hiroshi Akiyama

Shinji Nishihara

Hiroshi Kawakami

Hiroshi Hasegawa

Saburo Kanai

Masahiro Tadokoro

Tadamitsu Kanekiyo

Yoshifumi Tahara

Kazuyuki Tsunokuni

Masayuki Tomoyasu

Katsuya Watanabe

Yutaka Omoto

Takazumi Ishizu

Kazushi Tomita

Tsuyoshi Yoshida

Masataka Kasai

Ryoji Hamasaki

A semiconductor integrated circuit device is provided which includes an active region, a shallow groove isolation adjacent to the active region, and a semiconductor element formed in the active region and having a gate. The sum of a width of the active region and a width of the shallow groove isolation constitutes a minimum pitch in the direction of a gate width of the gate, and the width of the active region is set larger than one-half of the minimum pitch.

Semiconductor integrated circuit device and a method of manufacturing the same

A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the steps of installing the sample on a sample board in a vacuum container, generating a plasma that consists of a mixture of halogen gas and adhesive gas inside the vacuum container, applying a radio frequency bias voltage having a frequency ranging from 200 kHz to 20 MHz on the sample board, and controlling a periodic on-off of the radio frequency bias voltage with an on-off control frequency ranging from 100 Hz to 10 kHz.

Sample surface processing method

A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodesare formed via a gate insulating filmon the main surface of a semiconductor substrate, and on side surfaces of each of the gate electrodes there is formed a first side wall spacercomposed of silicon nitride and a second side wall spacercomposed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holesandin a self-matching manner with respect to the first side wall spacersand connecting portion is formed connecting a conductorto a bit line BL. In addition, in the N channel MISFETs Qnand Qn, and in the P channel MISFET Qpin areas other than the DRAM memory cell area, high density N-type semiconductor areasandare formed, as well as a high density P-type semiconductor areais formed in a self-matching manner with respect to the second side wall spacers

Semiconductor integrated circuitry and method for manufacturing the circuitry

A plasma processing method for etching a sample having a gate oxide film which generates a plasma in a vacuum chamber using electromagnetic waves, applies an rf bias power to the sample, turns off the rf bias power before a charged voltage of the sample reaches a breakdown voltage of the gate oxide film, turns on the rf bias power after the charged voltage of the sample has substantially dropped and repeats the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time, and the plasma is generated by continuously supplying power to enable generation of the plasma during the repeated turning on and off of the rf bias power.

Surface processing method of a specimen and surface processing apparatus of the specimen

Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.

Method and apparatus for processing samples

According to the present invention, there is provided a sample surface treating apparatus for processing a fine pattern by plasma etching, including a stage provided in a chamber, on which a sample to be subjected to a surface treatment is placed; etching gas supply source for continuously supplying an etching gas for plasma generation into the chamber; a plasma generator for generating a high-density plasma in the chamber; a bias power supply for applying a bias voltage of 100 kHz or higher to the stage independently of the plasma generation; and a pulse modulator for modulating the bias power supply at a frequency of 100 Hz to 10 kHz, wherein a surface treatment in which the minimum feature size is 1 &#x3bc;m or smaller is performed on the sample placed on the stage.

Method and apparatus for treating surface of semiconductor

A fabrication method of a semiconductor integrated circuit device comprises, in an SAC process or HARC process, subjecting a semiconductor substrate to plasma etching to make contact holes in an oxide film made of a silicon oxide film formed on the semiconductor substrate. For improving the ease-in-etching property of the silicon oxide film and selectivity to a nitride film, a residence time of an etching gas within a chamber is so set as to be in a range where selectivity to an insulating film made of silicon nitride is improved by using etching conditions of a low pressure and a large flow rate of the etching gas of CH/O/Ar.

Fabrication method of semiconductor integrated circuit device

An SOG film obtained by heat-treating a polysilazan type SOG film at high temperature of about 800&deg; C. is used as a planarized insulating film to be formed on the gate electrode ( ; see FIGS. and ) of a MISFET (Qs, Qn, Qp) A polysilazan SOG film ( ) not subjected to such a heat treatment is used as interlayer insulating film arranged among upper wiring layers ( ).

Method of manufacturing semiconductor integrated circuit device having insulating film formed from liquid substance containing polymer of silicon, oxygen, and hydrogen

A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes are formed via a gate insulating film on the main surface of a semiconductor substrate , and on side surfaces of each of the gate electrodes there is formed a first side wall spacer composed of silicon nitride and a second side wall spacer composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes and in a self-matching manner with respect to the first side wall spacers and connecting portion is formed connecting a conductor to a bit line BL. In addition, in the N channel MISFETs Qn and Qn , and in the P channel MISFET Qp in areas other than the DRAM memory cell area, high density N-type semiconductor areas and are formed, as well as a high density P-type semiconductor area is formed in a self-matching manner with respect to the second side wall spacers

A method and apparatus of treating a surface of a sample. A sample is arranged on a stage provided in a chamber, an etching gas is continuously supplied into the chamber and a plasma is generated from the etching gas. An rf bias at a frequency of 100 kHz or higher is applied to the stage independently of the generation of the plasma, and the rf bias is modulated at a frequency of 100 Hz to 10 kHz. Thereby, a surface treatment in which a minimum feature size is 1 &mgr;m or smaller is performed on the sample.

An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.

Semiconductor integrated circuit and method for manufacturing the same

Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.

Semiconductor integrated circuit device and method of manufacturing involving the scale-down width of shallow groove isolation using round processing

A plasma processing method for etching a sample having a gate oxide film includes generating a plasma in a vacuum chamber using electromagnetic waves, applying an rf bias power to the sample, turning off the rf bias power before a charged voltage of the sample reaches a breakdown voltage, turning on the rf bias power after the charged voltage of the sample has substantially dropped, and repeating the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time.

Specimen surface processing method

Method for processing surface of sample

Growing community of inventors

Kokubunji, Japan

Masayuki Kojima