Sanyo Electric Co., Ltd.

Tottori Sanyo Electric Co., Ltd.

Masayuki Koga

Yasushi Miyajima

Ryuji Nishikawa

Mitsugu Kobayashi

Katsuya Kihara

Michiru Senda

Ryoichi Yokoyama

Koji Marumo

Atsushi Wada

Keiichi Sano

Kazuto Noritake

Masahiro Okuyama

Toshifumi Yamaji

Isao Akima

Kenya Uesugi

Kuni Yamamura

When a selection TFT and a correction TFT are turned on, a data voltage of a data line is stored in a storage capacitor as a gate voltage of a driving TFT. After turning off the selection TFT, a voltage of a capacitor line SC falls, thereby turning on the driving TFT to supply a driving current to an organic EL element. The correction TFT is in the ON state before the capacitor line SC falls, and is turned off in the course of the fall of the line. Consequently, the capacitance of the correction TFT changes during the fall of the gate voltage, and the gradient of the gate voltage fall of the driving TFT is changed, thereby setting the gate voltage after the capacitor line SC falls in accordance with variation in threshold of the driving TFT. Particularly by disposing the driving TFT and the correction TFT adjacent to each other, the two TFTs are provided with the same properties to achieve effective correction.

Pixel circuit and display device

A display allowing further miniaturization when including a plurality of display panels is obtained. This display comprises a first display panel formed on a substrate and a second display panel formed on the same substrate on a region different from that formed with the first display panel. Thus, the display can be further miniaturized as compared with that having a first display panel and a second display panel formed on different substrates.

Display including a plurality of display panels

When a switching TFT is switched on, a data voltage on a data line is stored in a storage capacitor as a gate voltage of a driver TFT. In this state, a voltage on a pulse drive line is caused to fall. AMOS type capacity element having a second electrode connected to a reference voltage is connected to a gate of the driver TFT. The MOS type capacity element is in an ON state before a fall of the pulse drive line and becomes an OFF state during the fall, and a capacitance changes at the switching of ON state to the OFF state. Therefore, the slope of fall of the gate voltage changes, and the gate voltage after the fall on the pulse drive line can be corrected corresponding to the variation in the threshold values among driver TFTs.

When the orientation of liquid crystal molecules in a pixel are divided by an orientation divider, a boundary of the orientation is produced at any part of the pixel. A drain signal line () is formed to overlap with the boundary so that a light-shielding region in the pixel is decreased and an aperture ratio can be improved. Leakage of light caused when the orientation is disturbed can be shielded by the drain signal line (), and contrast can be enhanced. The orientation divider can be an orientation control window (), an orientation control slope () or the like.

Liquid crystal display device having particular drain lines and orientation control window

Liquid crystal display device having particular orientation control window

When a gate voltage having a rectangular-shaped pulse is supplied, the voltage of a pixel electrode is pulled down and fluctuated by a fall of the gate voltage due to a parasitic capacitor formed between a gate line and the pixel electrode, i.e. a so-called drop voltage is generated. As the drop voltage depends on a time constant of a change in the gate voltage, it can be diminished by smoothing the falling edge of the gate voltage. This is achieved by, for example, providing a current discharging transistor of a gate driverwith a small channel width to decrease the maximum current value. By utilizing such a gate voltage, a liquid crystal display device with a small drop voltage can be provided, even when the capacitance of the parasitic capacitor is great.

Display device of active matrix type

Information is not written in through channel dope, but through the difference of ions implanted into the impurity region of a semiconductor layer. Each memory element has a pair of the thin film transistors. The memory element with '1' written on it and the memory element with '0' written on it are differentiated based on whether the thin film transistors of the pair belongs to the same conductivity type or different conductivity types. Also, when the write-in impurity region is formed adjacent the impurity region, it is possible to differentiate the memory elements based on whether a diode connected to the thin film transistor in series is formed or not. Since these elements can be produced without the ion-implantation through the gate electrode, it is possible to build a mask ROM on the glass substrate. Also, it is possible to differentiate the memory elements based on whether wiring contact holes are formed in the thin film transistor or not. This invention enables the formation of the memory element on the glass substrate to fabricate a mask ROM.

Semiconductor memory device

On an insulating substrate, there are formed a first gate electrode, a gate insulating film, a semiconductor film, and an interlayer insulating film. Above the interlayer insulating film, a TFT is formed having a second gate electrode connected to the first gate electrode. Then, a photosensitive resin is formed over the entire surface of the extant layers. Subsequently, first exposure is applied using a first mask, and second exposure is then applied using a second mask with a larger amount of light than used for the first exposure. The second mask has an opening at a position corresponding to a source. Thereafter, the photosensitive resin film is developed thereby forming a contact hole and a concave.

Manufacturing method for reflection type liquid crystal display

Two charge transfer passages of one TFT, which comprise two areas with island layers of p-Si intersecting at right angles and running from respective drain areas ND, PD to source areas NS, PS through an LD area LD and a channel area CH, are arranged non-parallel to each other. Even if a defective crystallization area R, which is caused due to uneven intensity in an irradiated area in laser annealing for forming p-Si of a p-Si TFT LCD, passes across the TFT area, and either of the transfer passages is defective, the remaining one operates normally, and the component characteristics are maintained as desired.

Display device and semiconductor device having laser annealed semiconductor elements

A data line driving circuit comprises a shift register for sequentially generating sampling pulses according to a clock pulse, a buffer connected to each stage of the shift register, and a sampling switch for sampling a data signal according to the sampling pulse outputted from the buffer. The buffer is provided with a logic gate for synchronizing the output of the shift register with the clock signal.

Data line driving circuit formed by a TFT based on polycrystalline

A shift register circuit includes a plurality of shift register blocks and a plurality of connecting sections that belong to a plurality of signal shifting systems. Each of the shift register blocks includes a plurality of shift register groups, each of which belongs to the plurality of signal shifting systems. Each of the connecting sections is provided to mutually connect the shift register groups belonging to the associated signal shifting system. The plurality of shift register blocks and the plurality of connecting sections are arranged in a line in the shift register circuit. Further, the plurality of connecting sections are separated by at least two connecting section groups in that line arrangement with at least one of the shift register blocks located between the connecting section groups.

Shift register circuit and display unit incorporating the same

A shift register has four systems of shift registers for bidirectional scans and normal/redundant lines. The respective systems of shift registers are divided into blocks, so that transmission circuits are provided therebetween. The transmission circuits form switching circuits through transfer gates. The transmission circuits receive output signals from both of the shift registers for the normal/redundant lines, and output only normal output signals to next stage shift registers in accordance with control signals.

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Anpachi-gun, Japan

Masayuki Koga