Kabushiki Kaisha Toshiba

Masayuki Kawasaki

Akihiro Sueda

Hidehiko Tachibana

Yasunori Kuwasima

Kiyomitsu Takatani

Syuji Katsuki

A booster circuit device comprises: a liquid crystal drive circuit (14) whose dissipated current changes; a timing circuit (11) for outputting a select signal according to the dissipated current of the liquid crystal drive circuit; a drive signal select circuit (12) for selecting and outputting any one of at least two drive signals CLK of different frequencies on the basis of the select signal outputted by the timing circuit (11); and a booster circuit (13) for supplying a supply voltage to the liquid crystal drive circuit (14) on the basis of the drive signal CLK outputted by the drive signal select circuit (12). Since any of the drive signals CLK of different frequencies can be selected and applied to the booster circuit (13) according to the dissipated current of the liquid crystal drive circuit (14), it is possible to reduce the current dissipation of the booster circuit, that is the current dissipation of the whole booster circuit device can be reduced markedly.

Booster circuit device

Two p-channel MOS transistors are inserted in series between the positive power supply and the output terminal, whereas two n-channel MOS transistors are inserted in series between the output terminal and the negative power supply. Across the source and drain of one of the p-channel MOS transistors, a first diode is connected in parallel in the forward direction. Similarly, across the source and drain of one of the n-channel MOS transistors, a second diode is connected in parallel in the forward direction.

CMOS output circuit having controlled slope

An analog signal input circuit comprises a plurality of input terminals, an output node, a plurality of p-type first FETs inserted between the input terminals and the output node, and a plurality of n-type second FETs inserted between the input terminals and the output node. The gate terminals of the first FETs are supplied with first control signals, and the substrates thereof are connected to a positive potential power source terminal. The source of one first FET is connected to the drain of another. The gate terminals of the second FETs are supplied with second control signals. The second FETs have parasitic bipolar transistors which function as PN junctions whose conduction directions are opposite with reference to each other. The source of one second FET is connected to the drain of another.

Growing community of inventors

Ooita, Japan

Masayuki Kawasaki