Kabushiki Kaisha Toshiba

National Institute for Materials Science

Kioxia Corporation

Panasonic Holdings Corporation

Masayuki Katagiri

Tadashi Sakai

Yuichi Yamazaki

Naoshi Sakuma

Mariko Suzuki

Makoto Wada

Hisao Miyazaki

Akihiro Kajita

Atsuko Sakata

Masayuki Kitamura

Ichiro Mizushima

Yasutaka Nishida

Takashi Yoshida

Takatoshi Yamada

Takashi Taniguchi

Kenji Watanabe

Satoshi Koizumi

Hisao Kanda

Nesladek Milos

Tomio Ono

Toshiyuki Sakuma

Taishi Ishikura

Akiyoshi Ogane

Akinao Kitahara

Shintaro Sato

Kazuya Murata

Naohsi Sakuma

A solar cell assembly includes a plurality of solar cells and an inter-cell region provided between adjacent ones of the solar cells included in the plurality of solar cells. Each of the solar cells and the inter-cell region includes: a semiconductor substrate having a first conductivity type and having a first main surface and a second main surface that face away from each other; a first amorphous semiconductor layer having a second conductivity type and being provided on a first main surface side of the semiconductor substrate; an insulating layer provided on part of the first amorphous semiconductor layer; and a first transparent conductive film provided on the first amorphous semiconductor layer so as to cover the insulating layer. In a plan view of the solar cell assembly, the insulating layer is provided along the inter-cell region and partially overlapping the inter-cell region.

Solar cell assembly and method of manufacturing solar cell

According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

Method for manufacturing a semiconductor device

A graphene wiring structure of an embodiment has: an amorphous or polycrystalline insulating film; and a multilayer graphene on the insulating film. The multilayer graphene including a plurality of graphene crystals having a zigzag direction is oriented at 17 degrees or less with respect to an electric conduction direction on the insulating film.

Method for manufacturing graphene wiring structure and method for manufacturing wiring structure

Graphene wiring structure and semiconductor device using the same

A graphene wiring structure of an embodiment has a multilayered graphene having a plurality of planar graphene sheets laminated, and a first interlayer substance being a metal oxyhalide between the plurality of planar graphene sheets.

Graphene wiring structure and method for manufacturing graphene wiring structure

A graphene wiring structure of an embodiment has a substrate, a metal part on the substrate, multilayered graphene connected to the metal part, a first insulative film on the substrate, and a second insulative film on the substrate. The metal part is present between the first insulative film and the second insulative film. Edges of the multilayered graphene are connected to the metal part. A side face of the first insulative film vertical to the substrate opposes a side face of the second insulative film vertical to the substrate. A first outer face of the multilayered graphene is in physical contact with a first side face of the first insulative film vertical to the substrate. A second outer face of the multilayered graphene is in physical contact with a second side face of the second insulative film vertical to the substrate.

Graphene wiring of an embodiment has a graphene intercalation compound including a multilayer graphene having graphene sheets stacked therein and an interlayer substance disposed between layers of the multilayer graphene, and an interlayer cross-linked layer connected to a side surface of the multilayer graphene. The interlayer cross-linked layer has a cross-linked molecular structure including multiple bonded molecules cross-linking the graphene sheets included in the multilayer graphene.

Graphene wiring and method for manufacturing the same

A graphene wring structure of an embodiment includes multilayer graphene, a first interlayer compound existing in an interlayer space of the multilayer graphene, and a second interlayer compound existing in the interlayer space of the multilayer graphene. The second interlayer compound containing at least one of an oxide, a nitride and a carbide.

Graphene wiring structure and manufacturing method thereof

According to one embodiment, a semiconductor device includes a metal interconnect and a graphene interconnect which are stacked to one another.

Semiconductor device and method of manufacturing the same

A graphene wiring has a substrate, a catalyst layer on the substrate, a graphene layer on the catalyst layer, and a dopant layer on a side surface of the graphene layer. An atomic or molecular species is intercalated in the graphene layer or disposed on the graphene layer.

Graphene wiring

A semiconductor device of an embodiment includes: a substrate on which a semiconductor circuit is formed; an interlayer insulating film in which a contact hole is formed on the substrate; a catalyst metal film on a side wall of the contact hole; catalyst metal particles on a bottom of the contact hole; graphene on the catalyst metal film; and carbon nanotubes, which penetrates the contact hole, on the catalyst metal particles.

A semiconductor device according to an embodiment includes: a first diamond semiconductor layer of a first conductivity type including a main surface having a first plane orientation; a trench structure formed in the first diamond semiconductor layer; a second diamond semiconductor layer formed on the first diamond semiconductor layer in the trench structure and having a lower dopant concentration than the first diamond semiconductor layer; a third diamond semiconductor layer of a second conductivity type formed on the second diamond semiconductor layer and having a higher dopant concentration than the second diamond semiconductor layer; a first electrode electrically connected to the first diamond semiconductor layer; and a second electrode electrically connected to the third diamond semiconductor layer.

Semiconductor device

A graphene wiring of an embodiment includes graphene, first conductive layers, second conductive layers, and a third conductive layer. The first conductive layers are connected to first sides of the graphene opposite to each other in a longitudinal direction of the wiring. The second conductive layers are connected to second sides of the graphene opposite to each other in a widthwise direction of the wiring. The third conductive layer is connected to a top surface of the graphene. The first and second conductive layers are connected to each other.

Growing community of inventors

Kawasaki, Japan

Masayuki Katagiri