Elpida Memory, Inc.

Nec Corporation

Asahi Kasei Kabushiki Kaisha

Kobe University

Asahi Kasei Fibers Corporation

Kabushiki Kaisha Toshiba

Masayuki Kaneda

Takeshi Hashimoto

Yutaka Ito

Daisuke Sato

Toru Morita

Toshihiro Yoshii

Shigeo Takeuchi

Hideto Matsuyama

Masami Enda

Yumi Yaita

Takashi Komatsu

Nagayoshi Ichikawa

Ichiro Inami

Takeshi Kanasaki

Eiji Yamasaki

Masahiro Yasukawa

A forward osmosis membrane characterized in that a thin membrane layer having the performance of a semi-permeable membrane is laminated on a polyketone support layer.

Forward osmosis membrane and forward osmosis treatment system

To provide a polyketone porous film having heat resistance and chemical resistance and useful as a filter for filtration having a high particle collection efficiency and as a battery or capacitor separator having a low permeation resistance to ion and the like. A polyketone porous film comprising from 10 to 100 mass % of a polyketone as a copolymer of carbon monoxide and one or more olefins, wherein the polyketone porous film has a pore formed only by a polyketone, the pore diameter uniformity parameter as a value obtained by dividing the standard deviation of the pore diameter in the pore by an average pore diameter is from 0 to 1.0, and the average through hole diameter of the polyketone porous film is from 0.01 to 50 &#x3bc;m.

Polyketone porous film

A semiconductor memory device including an on-chip ECC circuit and having a data retention mode which includes, in the order of state transition, an encoding state EEST by an error correction circuit in which the error correction circuit carries out calculation of parity bits of data of the memory cells, a burst self-refresh state BSST in which the memory cells are self-refreshed in a burst with a period shorter than in ordinary self-refresh, a power-off state PFST in which an internal power supply circuit is partially turned off, a power-on state PNST in which the internal power supply circuit, partially turned off, is turned on, and a decoding state EDST by the error correction circuit in which the error correction circuit corrects errors of the memory cells. In case a command for exiting from the data retention mode in the encoding state, transition may be made to an idle state IST so that re-entry may be made from the decoding state EDST to the BSST.

Semiconductor memory device

A refresh counter circuit generating a row address during refresh operation for the memory device which has a normal area for storing data bits and a parity area for storing parity bits, including; n-stage counter which generates the row address corresponding to an address space of the normal area represented by n bits and the parity area represented by m (m&#x3c;n) bits; an area discriminating circuit which generates an area discriminating signal; a first switching circuit for switching between a first connected state in which all stages of the counter are connected and a second connected state in which a n&#x2212;m bits counter portion is disconnected from the counter; and an automatic reset circuit which generates a reset signal so that the count operation in the normal area is discriminated by the discriminating signal when stopping of the refresh operation in the second connected state.

Refresh counter circuit and control method for refresh operation

In a divider for dividing a dividend by a divisor to calculate a quotient and a remainder, the divisor being a natural number which is a constant, each of the dividend, the quotient, and the remainder being an integer which is not less than zero, first through N-th comparing circuits compare the dividend with first through N-th predetermined constants. An n-th predetermined constant is equal to n times as large as the divisor, where n is variable between 1 and N, both inclusive. The first through the N-th comparing circuit produce first through N-th comparison result signals. A decoder decodes a combination of the first through the N-th comparison result signals into first and second partial decoded signals. The first partial decoded signal is equal to the quotient. The second partial decoded signal is equal to lower bits of a product of the quotient and the divisor. A subtracter subtracts the second partial decoded signal from lower bits of the dividend to produce the remainder.

Fast divider for a constant divisor

Growing community of inventors

Tokyo, Japan

Masayuki Kaneda