Renesas Electronics Corporation

Renesas Technology Corp.

Daiichi Pharmaceutical Co., Ltd.

Hitachi, Ltd.

Astellas Pharma Gmbh

Hochiki Corporation

Niles Parts Company, Ltd.

Yazaki Corporation

Hitachi High-tech Corporation

Daiichi Sankyo Company, Limited

Waseda University

Hochiki Kabushiki Kaisha

National Center of Neurology and Psychiatry

Masayuki Ito

Junichi Nishimoto

Fumio Arakawa

Naoki Kosugi

Makoto Toda

Kunio Uchiyama

Yasuhiro Sato

Susumu Narita

Osamu Nishii

Tatsuya Kamei

Hideki Sugimoto

Hideki Kubota

Satoshi Komoriya

Noriyasu Haginoya

Tsutomu Nagata

Yoshiyuki Tenda

Takayasu Nagahara

Satoru Miyauchi

Syozo Kobayashi

Akiyoshi Mochizuki

Shinsuke Nakao

Haruhiko Horino

Takayoshi Endo

Masanori Suzuki

Osamu Matsumoto

Masanori Saito

Tamio Watanabe

Takahiro Yoneda

Takahiro Irita

Koji Goto

Keiji Kimura

Toshihiro Hattori

Hironori Kasahara

Ryota Watanabe

Hajime Yamashita

Takashi Sakamaki

Saneaki Tamaki

Toshiharu Yoshino

Mark Hill

Tsuyoshi Sotome

Kunihiko Nishiyama

Yoshiyuki Nakada

Takao Koike

Kayoko Motoki

Takanori Yasukouchi

Thomas Edison Chua Yu

Yutaka Yoshida

Jun Hasegawa

Tomohisa Akamatsu

The automatic analyzer includes a first storage device that stores sample information including a measurement result of a reaction solution for each sample and a second storage device that stores the sample information on at least a part of the samples among the sample information stored in the first storage device, in which when the automatic analyzer reaches a predetermined operation state, the control device performs a backup process of backing up the sample information on the samples satisfying a predetermined backup condition from the first storage device to the second storage device, and deleting the sample information on the backed up samples from the first storage device.

Automatic analyzer

[Problem] Provided is an anti-human BDCA-2 antibody for preventing or treating an autoimmune disease by binding to a human BDCA-2 to control the function of a plasmacytoid dendritic cell through human BDCA-2. [Means for Solution] The present inventors have investigated anti-human BDCA-2 antibodies, and as a result, they have provided an anti-human BDCA-2 antibody comprising a heavy chain variable region consisting of the amino acid sequence of amino acid numbers 1 to 120 of SEQ ID NO: 2 and a light chain variable region consisting of the amino acid sequence of amino acid numbers 1 to 109 of SEQ ID NO: 4, a heavy chain variable region consisting of the amino acid sequence of amino acid numbers 1 to 120 of SEQ ID NO: 6 and a light chain variable region consisting of the amino acid sequence of amino acid numbers 1 to 108 of SEQ ID NO: 8, and a heavy chain variable region consisting of the amino acid sequence of amino acid numbers 1 to 122 of SEQ ID NO: 10 and a light chain variable region consisting of the amino acid sequence of amino acid numbers 1 to 108 of SEQ ID NO: 12.

Anti-human BDCA-2 antibody

According to an embodiment, an information processing apparatus includes a plurality of cores, a shared resource that can be shared by the plurality of cores, and local registers that store configuration information peculiar to the respective cores. The shared resource is provided independently from the plurality of cores. The local registers are provided to the respective cores. This makes it possible to provide an information processing apparatus that can suppress increase in hardware resources even when the number of cores composing a multi-core system increases.

Information processing apparatus

Part of a plurality of ways are selected from among the ways according to a value of select data created based on tag address information which is part of address information, and cache tags are read. Further, when performing cache fill, the cache memory performs the cache fill on a cache entry selected from part of the ways according to the value of the select data. For select data used for selecting a way, e.g. parity data in connection with tag address information is used. A way to read a cache tag from is selected based on a value of parity data and further, the way of a cache entry to perform cache fill on is selected.

Data processing device utilizing way selection of set associative cache memory based on select data such as parity data

A memory protection circuit includes a memory access information register that stores memory access information related to memory areas which can be accessed by respective virtual machines, and an access determination circuit that determines whether to allow the virtual machines to access the memory areas based on a memory address when each of the virtual machines accesses a memory, information related to the virtual machines that access the memory, and the memory access information stored in the memory access information register. The memory access information register may comprise memory area setting registers and memory area allocation registers. A register access information register may indicate register areas which can be accessed by the virtual machines. A virtual machine scheduler or thread scheduler may determine an order of instructions to be executed.

Memory protection circuit, method and processing unit utilizing memory access information register to selectively allow access to memory areas by virtual machines

A semiconductor device comprising: a first processor; a second processor; a first delay circuit delaying a signal input into the first processor by a predefined number of cycles and inputting the signal into the second processor; a first compression circuit compressing a signal of n-bit width from the first processor into a signal of m-bit width (m&#x3c;n) and outputting the signal of m-bit width; a second compression circuit compressing a signal of n-bit width from the second processor into a signal of m-bit width and outputting the signal of m-bit width; a second delay circuit delaying the signal from the first compressor by the predefined number of cycles and outputting the delayed signal; and a coincidence comparison circuit comparing bit-wise the corresponding bits of the signals from the second delay circuit and from the second compression circuit to check whether the corresponding bits coincide with each other or not.

Semiconductor device

The present invention relates to a novel compound having an effect of inhibiting production/secretion of &#x3b2;-amyloid protein. The present invention provides a compound represented by the general formula (1): 

Pyridylmethylsulfone derivative

Each of processors has a barrier write register and a barrier read register. Each barrier write register is wired to each barrier read register by a dedicated wiring block. For example, a 1-bit barrier write register of a processor is connected, via the wiring block, to a first bit of each 8-bit barrier read register contained in the processors, and a 1-bit barrier write register of another processor is connected, via a wiring block, to a second bit of each 8-bit barrier read register contained in the processors. For example, a processor writes information to its own barrier write register, thereby notifying synchronization stand-by to the other processors and reads its own barrier read register, thereby recognizing whether the other processors are in synchronization stand-by or not. Therefore, a special dedicated instruction is not required along barrier synchronization processing, and the processing can be made at a high speed.

Multiprocessor system and method of synchronization for multiprocessor system

A processing load of a high performance application processing such as a voice, an image and the like is reduced, and a processing capacity of a base band processing is improved. A semiconductor integrated circuit device used in a mobile communication system such as a cellular phone is provided with a base band CPU block performing a base band processing for executing a base band protocol stack, an application system CPU block executing a high-level OS and controlling applications other than the base band processing, an application real-time CPU block executing a real-time OS and the like and controlling an image/voice processing, all of which are formed on one semiconductor chip. Further, internal high-speed buses to which these CPU blocks are connected are respectively connected via bridges.

Semiconductor integrated circuit device

A data processor arranged so that a block transfer control unit () can initiate block transfer in response to the execution of a particular instruction by a CPU, in order to increase the speed and efficiency of the data transfer between a CPU-accessible internal memory () and an external memory (). When an address specified by the addressing field coincides with an address mapped to the internal memory, the particular instruction sets a logical address as one of the transfer source or transfer destination addresses of the data block transfer. The internal memory is allotted to a part of virtual address space; the internal memory allotted so is associated with the physical address space, to which the external memory set as the other address is allotted, by a process in which a TLB is used when the MMU is in ON, and a given register is used when the MMU is in OFF.

Data processor with block transfer control

Provided are novel compounds having an inhibitory activity against production or secretion of &#x3b2;-amyloid protein. They embrace compounds represented by the following formula (1): and capable of being replaced with a variety of substituents; and salts thereof, and solvates of any one of them.

&#x3b2;-amyloid protein production/secretion inhibitor

In performing address translation from a virtual address space to a physical address space, when the virtual address space is divided into an area (P), which is subjected to the address translation by TLB, and areas (Pand P), which are fixedly mapped to the physical address without being subjected the address translation, future extension of the physical address become difficult. A data processor comprises an address translation unit ATU that receives virtual address output from the CPU and outputs a physical address; the ATU includes a first translation lookaside buffer UTLB, a second translation lookaside buffer DTLB, a control circuit TLB_CTL that selects one of a first and a second translation lookaside buffers and performs address translation in accordance with an area of an address space in the virtual address. Since it is adapted so that the areas (Pand P), which are conventionally mapped fixedly by hardware, are subjected to the address translation by the DTLB, it is possible to extend a size of the physical address space later without changing the hardware.

Data processor and IP module for data processor

The data processor has a set-associative cache memory capable of performing associative operation using tag information for an indexed cache line. The cache memory includes way prediction part for performing a selection of a way based on the prediction in parallel with the associative operation, generation part for generating way selection determining information based on the associative operation using the subsequent access address during a penalty cycle caused by a prediction miss of the way prediction part, and control part for making a way selected for the subsequent access address after the penalty cycle on the basis of the way selection determining information. Since a way to be hit at the subsequent cache access can be predetermined during the preceding penalty cycle, the cumulative number of penalty cycles can be reduced.

Data processor for reducing set-associative cache energy via selective way prediction

Growing community of inventors

Tokyo, Japan

Masayuki Ito