Mitsubishi Electric Corporation

Mitsubishi Denki Kabushiki Kaisha

General Electric Company

Masayuki Imaizumi

Naruhisa Miura

Yasuhiro Kagawa

Akihiko Furukawa

Shiro Hino

Yoichiro Tarui

Yuji Abe

Kenichi Ohtsuka

Shuhei Nakata

Rina Tanaka

Yukiyasu Nakao

Hiroshi Watanabe

Yutaka Fukui

Naoki Yutani

Tomokatsu Watanabe

Ken-ichi Ohtsuka

Hiroshi Sugimoto

Masayoshi Tarutani

Yoshinori Matsuno

Sunao Aya

Shoyu Watanabe

Yuji Ebiike

Masayuki Furuhashi

Toshikazu Tanioka

Tetsuya Takami

Keiko Fujihira

Mitsuru Kobayashi

Takeharu Kuroiwa

Shohei Yoshida

Kohei Ebihara

Kenji Hamada

Kazuyasu Nishikawa

Nobuyuki Tomita

Kenichi Hamano

Eisuke Suekawa

Shinichi Kinouchi

Kenichi Kuroda

Hiroshi Nakatake

Tatsuo Oomori

Yoichiro Mitani

Hiroaki Okabe

Takao Sawada

Kenichi Otsuka

Hiroaki Sumitani

Tomoaki Furusho

Kiyomi Abeshima

Keiko Sakai

A gantry housingcomprises a front cover, a main cover, a rear cover, and a scan window. The scan windowhas a PolyCarbonate (PC) sheet, and elastic membersand. The front coverhas a receiving portionin which the elastic memberis disposed, and a reinforcing portionfor reducing deformation of the PC sheet; the rear coverhas a receiving portionin which the elastic memberis disposed, and a reinforcing portionfor reducing deformation of the PC sheet

Gantry housing, and medical apparatus

A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery below and horizontally overlapping a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.

Silicon carbide semiconductor device

An insulated gate silicon carbide semiconductor device includes: a drift layer of a first conductivity type on a silicon carbide substrate of 4H type with a {0001} plane having an off-angle of more than 0&#xb0; as a main surface; a first base region; a source region; a trench; a gate insulating film; a protective diffusion layer; and a second base region. The trench sidewall surface in contact with the second base region is a surface having a trench off-angle of more than 0&#xb0; in a &#x3c;0001&#x3e; direction with respect to a plane parallel to the &#x3c;0001&#x3e; direction. The insulated gate silicon carbide semiconductor device can relieve an electric field of a gate insulating film and suppress an increase in on-resistance and provide a method for manufacturing the same.

Insulated gate silicon carbide semiconductor device and method for manufacturing same

A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.

A method for manufacturing a semiconductor device capable of reducing an ON resistance. In the present invention, a drift layer is formed on a substrate. An ion implanted layer is formed in a surface of the drift layer. A surplus carbon region is formed in the drift layer. The drift layer is heated. In a case where the surplus carbon region is formed, the surplus carbon region is formed in a region deeper than an interface between the ion implanted layer and the drift layer. In a case where the drift layer is heated, impurity ions of the ion implanted layer are activated to form an activation layer, and interstitial carbon atoms are dispersed toward the activation layer.

SiC semiconductor device having pn junction interface and method for manufacturing the SiC semiconductor device

There is provided a trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device has a gate electrodeembedded into a trenchpenetrating a base region. The gate electrodeis disposed into a lattice shape in a planar view, and a protective diffusion layeris formed in a drift layerat the portion underlying thereof. At least one of blocks divided by the gate electrodeis a protective contact regionon which the trenchis entirely formed. A protective contactfor connecting the protective diffusion layerat a bottom portion of the trenchand a source electrodeis disposed on the protective contact region

Trench-gate type semiconductor device and manufacturing method therefor

A silicon-carbide semiconductor device that relaxes field intensity in a gate insulating film, and that has a low ON-resistance. The silicon-carbide semiconductor device includes: an n-type silicon-carbide substrate; a drift layer formed on a topside of the n-type silicon-carbide substrate; a trench formed in the drift layer and that includes therein a gate insulating film and a gate electrode; a p-type high-concentration well region formed parallel to the trench with a spacing therefrom and that has a depth larger than that of the trench; and a p-type body region formed to have a depth that gradually increases when nearing from a position upward from the bottom end of the trench by approximately the thickness of the gate insulating film at the bottom of the trench toward the lower end of the p-type high-concentration well region.

Silicon-carbide semiconductor device and manufacturing method thereof

A device that increases a value of current flowing through a whole chip until a p-n diode in a unit cell close to a termination operates and reduces a size of the chip and a cost of the chip resulting from the reduced size. The device includes a second well region located to sandwich the entirety of a plurality of first well regions therein in plan view, a third separation region located to penetrate the second well region from a surface layer of the second well region in a depth direction, and a second Schottky electrode provided on the third separation region.

Semiconductor device

A source region of a MOSFET includes: a source contact region connected to a source pad; a source extension region adjacent to a channel region in a well region; and a source resistance control region arranged between the source extension region and the source contact region. The source resistance control region is different in an impurity concentration from the source extension region and the source contact region. These three regions are connected in series between the source pad and the channel region in the well region.

A semiconductor device capable of reducing ON-resistance changes with temperature, including a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type formed on the semiconductor substrate, a first well region of a second conductivity type formed in the front surface of the drift layer, a second well region of the second conductivity type formed in the front surface of the drift layer, and a gate structure that is formed on the front surface of the drift layer and forms a channel in the first well region and a channel in the second well region. A channel resistance of the channel formed in the first well region has a temperature characteristic that the channel resistance decreases with increasing temperature and a channel resistance of the channel formed in the second well region has a temperature characteristic that the channel resistance increases with increasing temperature.

Vertical MOSFET device with steady on-resistance

In a JBS diode using a wide band gap semiconductor, the wide band gap semiconductor has a large built-in voltage, which sometimes causes difficulties for the pn diode portion to turn on, resulting in a problem that resistance to surge currents is not sufficiently ensured. In order to solve this problem, in the wide-band-gap JBS diode, a pn junction of the pn diode is formed away from the Schottky electrode, and well regions are formed so as to have a width narrowed at a portion away from the Schottky electrode.

Semiconductor device including well regions with different impurity densities

A silicon carbide semiconductor device that reduces an influence of an off-angle of a silicon carbide substrate on characteristics of the semiconductor device and achieves improved operational stability and reduced resistance. In a trench-gate silicon carbide MOSFET semiconductor device, a high-concentration well region is formed in a well region, and a distance from a first sidewall surface of a trench of the silicon carbide semiconductor to the high-concentration well region is smaller than a distance from a second sidewall surface of the trench to the high-concentration well region, the second sidewall surface facing the first sidewall surface of the trench through the gate electrode.

Silicon-carbide semiconductor device and method for manufacturing the same

It is expected that both reduction of the resistance of a source region and reduction of a leakage current in a gate oxide film be achieved in an MOSFET in a silicon carbide semiconductor device. A leakage current to occur in a gate oxide film of the MOSFET is suppressed by reducing roughness at an interface between a source region and the gate oxide film. If an impurity concentration is to become high at a surface portion of the source region, the gate oxide film is formed by dry oxidation or CVD process. If the gate oxide film is formed by wet oxidation, the impurity concentration at the surface portion of the source region is controlled at a low level.

Silicon carbide semiconductor device and method of manufacturing the same

Growing community of inventors

Tokyo, Japan

Masayuki Imaizumi