Kabushiki Kaisha Toshiba

Sandisk Corporation

Kabsuhiki Kaisha Toshiba

Masayuki Ichige

Kikuko Sugimae

Riichiro Shirota

Yuji Takeuchi

Atsuhiro Sato

Fumitaka Arai

Koji Hashimoto

Satoshi Tanaka

Seiichi Mori

Hiroaki Hazama

Michiharu Matsui

Toshitake Yaegashi

Hiroyuki Kutsukake

Yasuhiko Matsunaga

Koji Sakui

Yoshio Ozawa

Ichiro Mizushima

Akihito Yamamoto

Tatsuaki Kuji

Yoshihiko Saito

Akira Goda

Yukio Nishiyama

Naruhiko Kaji

Hirotaka Ogihara

Masaaki Higashitani

Takuya Futatsuyama

Tuan Duc Pham

Junya Matsunami

Makoto Sakuma

Akira Shimizu

Yoshiko Kato

Hisataka Meguro

Takuya Konno

This nonvolatile semiconductor memory device comprises a memory cell array configured having a plurality of memory mats arranged therein, each of the memory mats having a memory cell disposed therein at an intersection of a first line and a second line, the memory cell including a first variable resistance element. A third line extends through a plurality of the memory mats. A second variable resistance element is connected between the third line and the second line of each of the plurality of memory mats.

Nonvolatile semiconductor memory device

A nonvolatile memory device includes: a first interconnection extending in a first direction; a second interconnection extending in a second direction, and a lower end of the second interconnection being located above the first interconnection; a plurality of third interconnections extending in a third direction, and the third interconnections being arranged in the second direction; a current limitation layer provided between the second interconnection and the third interconnections; a metal ion source layer provided between the current limitation layer and the third interconnections; a resistance change layer provided between the current limitation layer and the third interconnections; and a selector provided between the first interconnection and the lower end of the second interconnection.

Non-volatile memory device and method for manufacturing same

A semiconductor memory includes: a plurality of active regions AA, AA, . . . , AA, which extend on a memory cell array along the column length; a plurality of non-uniformly arranged word line patterns WL, WL, . . . , extending along the row length; a plurality of select gate line patterns SG, SG, . . . , arranged parallel to the plurality of word line patterns; borderless contacts formed near the ends of the word line patterns on the memory cell array, in contact with part of an interconnect extended from the end of the memory cell array, but not in contact with interconnects adjacent to that interconnect; and bit line contacts formed within contact forming regions provided by removing part of the plurality of word line patterns and select gate line patterns through double exposure.

Semiconductor memory

A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.

Nonvolatile semiconductor memory

A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, first and second control gate electrode layers, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on a high voltage gate insulating film, a second inter-gate insulating film having an aperture, third and fourth control gate electrode layers, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on a second tunneling insulating film, a third inter-gate insulating film having an aperture, fifth and sixth control gate electrode layers, and a third metallic silicide film; and a liner insulating film directly disposed on source and drain regions of each of the memory cell transistor, the low voltage transistor, and the high voltage transistor.

Nonvolatile semiconductor memory and fabrication method for the same

According to one embodiment, a semiconductor memory device includes a plurality of memory cell blocks, a plurality of first wirings, a plurality of second wirings, and a contact. Each of the memory cell blocks includes a plurality of memory cell units. Each of the plurality of memory cell units includes a plurality of memory cells and is provided in a first direction at a prescribed spacing. The plurality of memory cell blocks is arranged in a second direction intersecting with the first direction. The plurality of first wirings extends in the second direction and is provided in the first direction at a prescribed spacing. The plurality of second wirings is provided at least one of above and below the first wiring. The contact is provided at both end portions of the second wiring in the second direction and connects the first wiring to the second wiring. A width dimension of the second wiring along the first direction is larger than a width dimension of the first wiring along the first direction.

Semiconductor memory device

Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions AA, AA, . . . , AA, which extend on a memory cell array along the column length; a plurality of word line patterns WL, WL, . . . , extend along the row length and are non-uniformly arranged; a plurality of select gate line patterns SG, SG, . . . , are arranged parallel to the plurality of word line patterns; borderless contacts are formed near the ends of the word line patterns on the memory cell array, and are in contact with part of an interconnect extended from the end of the memory cell array, but are not in contact with interconnects adjacent to that interconnect; and bit line contacts are formed within contact forming regions provided by removing part of the plurality of word line patterns and select gate line patterns through double exposure.

A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, a first and a second control gate electrode layer, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, a third and a fourth control gate electrode layer, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on the second tunneling insulating film, a third inter-gate insulating film having an aperture, a fifth and a sixth control gate electrode layer, and a third metallic silicide film; and a liner insulating film directly disposed on a first source and drain region of the memory cell transistor, a second source and drain region of the low voltage transistor, and a third source and drain region of the high voltage transistor.

A semiconductor integrated circuit device includes a cell well, a memory cell array formed on the cell well and having a memory cell area and cell well contact area, first wiring bodies arranged in the memory cell area, and second wiring bodies arranged in the cell well contact area. The layout pattern of the second wiring bodies is the same as the layout pattern of the first wiring bodies. The cell well contact area comprises cell well contacts that have the same dopant type as the cell well and that function as source/drain regions of dummy transistors formed in the cell well contact area.

EEPROM array with well contacts

A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, first and second control gate electrode layers, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, third and fourth control gate electrode layers, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on a second tunneling insulating film, a third inter-gate insulating film having an aperture, fifth and sixth control gate electrode layers, and a third metallic silicide film; and a liner insulating film directly disposed on first, second and third source and drain regions of the memory cell transistor, low voltage transistor, and high voltage transistor, respectively.

Nonvolatile semicondutor memory with metallic silicide film electrically connected to a control gate electrode layer

Growing community of inventors

Yokohama, Japan

Masayuki Ichige