Fujitsu Corporation

Masayuki Horie

Yukio Suda

Yasuhiro Ooba

Shiuji Sakakura

In a frame buffer monitoring method and device, information concerning a received frame is extracted, and a monitoring frame added to a start of the frame is written in a FIFO buffer. When the monitoring frame is read from the FIFO buffer, expectation information is generated from the information concerning the frame added to the start of the monitoring frame read, the expectation information is compared with the information concerning the frame included in the frame within the monitoring frame read, and whether or not the expectation information is consistent with the information concerning the frame is determined. As a result of the comparison, when it is determined that the expectation information is not consistent with the information concerning the frame, e.g. bits of an FCS within the frame which is determined to be inconsistent are inverted to be transmitted to a subsequent stage as a discarded frame or the frame is discarded. Also, a write destination address and a read source address for the FIFO buffer are initialized.

Frame buffer monitoring method and device

In a more effective data generation method and circuit used for 64B/66B encoding, when packet data, and head and tail information of the data packet are received, write user data in which a head and tail identifying bytes are respectively added to a head and a tail of the packet data based on the head and tail information is associated with control data indicating positions of both of the identifying bytes to be written in a memory sequentially from a predetermined address of the memory. From the predetermined address, user data by 8 bytes and the control data corresponding to the user data are sequentially read to be provided to a 64B/66B encoding circuit. During a period in which the reading can not be made, idle bytes for 8n bytes (n&#x2267;1) and control data indicating the idle bytes, or maintenance user data of 8n bytes (n&#x2267;2) in which the head and tail identifying bytes are respectively added to a head and a tail of the maintenance information and control data indicating positions of both of the identifying bytes are provided to the 64B/66B encoding circuit.

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Kawasaki, Japan

Masayuki Horie