Renesas Electronics Corporation

Mitsubishi Chemical Corporation

Sandisk Technologies Inc.

Nec Electronics Corporation

Masayuki Hiroi

Toshiyuki Takewaki

Daisuke Oshida

Teruyuki Mitsumori

Yasuaki Tsuchiya

Manabu Iguchi

Takuji Onuma

Yuka Nagao

Toshiji Taiji

Mieko Hasegawa

Takaharu Kunugi

Hironori Toyoshima

Hiroaki Nanba

Ichiro Honma

Yuki Mizutani

Hiroaki Takamura

Takuma Takimoto

Takumi Saito

Masaaki Higashitani

Hiroyuki Ogawa

Tatsuya Usami

Akira Matsumoto

Fumiaki Toyama

Akira Inoue

Chun-Ming Wang

Seiji Nagahara

Takashi Sakoh

Mamoru Nozomi

Noritaka Fukuo

Sadayuki Ohnishi

Tadashi Mizushima

Chenche Huang

Hiroaki Koketsu

Tomoko Nakagawa

Itaru Ogawa

Masami Tsurumori

Shunichirou Kurihara

Tooru Uenaka

Akihiko Yagishita

Shusuke Notsu

Masatoshi Okumura

A semiconductor structure includes a memory array including first and second bit lines and a sense amplifier circuit. The sense amplifier circuit includes a first sense amplifier array containing first active sense amplifier transistors that each have an active region having a first width, where the first active sense amplifier transistors are electrically connected to the first bit lines, and a second sense amplifier array including second active sense amplifier transistors that each have the active region having the first width, where the second active sense amplifier transistors are electrically connected to the second bit lines, and dummy active regions which are electrically inactive located between columns of the second active sense amplifier transistors.

Three-dimensional memory device including sense amplifiers having a common width and separation

A semiconductor structure includes a first-conductivity-type well located in a semiconductor substrate, a semiconductor active area region located adjacent to the a first-conductivity-type well, a first transistor including a source region, a drain region, a channel region located between the source region and the drain region, a gate dielectric layer located over the channel region and a gate electrode located over the gate dielectric layer, such that the transistor is located on the semiconductor active area region, and a cutoff gate electrode located over the semiconductor active area region, and between the first transistor and the first-conductivity-type well.

Cutoff gate electrodes for switches for a three-dimensional memory device and method of making the same

A first vertically alternating sequence of first insulating layers and first spacer material layers and a first-tier retro-stepped dielectric material portion are formed over a substrate. The first spacer material layers are formed as, or are subsequently replaced with, first electrically conductive layers. A second vertically alternating sequence of second insulating layers and second spacer material layers and a second-tier retro-stepped dielectric material portion are formed over the first vertically alternating sequence and the first-tier retro-stepped dielectric material portion. The second spacer material layers are formed as, or are subsequently replaced with, second electrically conductive layers. An opening is formed through the second vertically alternating sequence over the first-tier retro-stepped dielectric material portion, and is filled with a dielectric well structure. Contact via structures can be formed through the dielectric well structure and the first-tier retro-stepped dielectric material portion on the first electrically conductive layers.

Multi-tier three-dimensional memory device containing dielectric well structures for contact via structures and methods of forming the same

A three-dimensional semiconductor device includes bit lines formed in the lower-interconnect-level dielectric material layers located over a substrate, bit-line-connection via structures contacting a respective one of the bit lines, pillar-shaped drain regions contacting a respective one of the bit-line-connection via structures, an alternating stack of insulating layers and electrically conductive layers located over the pillar-shaped drain regions, and memory stack structures extending through the alternating stack. A source layer overlies the alternating stack, and is electrically connected to an upper end of each vertical semiconductor channel within a subset of the vertical semiconductor channels. Vertical bit line interconnections structures extending through the levels of the alternating stack may be eliminated by forming the bit lines underneath the alternating stack, and the footprint of the layout of the three-dimensional memory device may be reduced.

Three-dimensional memory device including bit lines between memory elements and an underlying peripheral circuit and methods of making the same

The present invention is directed to a semiconductor integrated circuit device that basically has a non-memory array area, a memory array area, and memory capacitors formed across lower embedded metal interconnection layers including a low-dielectric constant interlayer insulating film in the memory array area. In addition, a memory-periphery metal seal ring is provided in the lower embedded metal interconnection layers having at least the low-dielectric constant interlayer insulating film so as to surround the memory array area.

Memory and logic device and method for manufacturing the same

A structure is formed on a substrate, which includes a stack of alternating layers comprising insulating layers and electrically conductive layers and a plurality of memory stack structures extending through the stack. At least one bridge line structure is formed on top surfaces of a respective subset of the plurality of memory stack structures to provide local lateral electrical connection. At least one dielectric material layer is formed over the at least one bridge line structure and the plurality of memory stack structures. A plurality contact via structures is formed through the dielectric material layer. The plurality of contact via structures includes at least one first contact via structure contacting a top surface of a respective bridge line structure, and second contact via structures contacting a top surface of a respective memory stack structure.

Bridge line structure for bit line connection in a three-dimensional semiconductor device

In a semiconductor device including a seal ring area containing multiple seal rings are coupled to each other at equal intervals via bridge patterns, improper local relocation of bridge patterns may reduce the reliability of the semiconductor device. A semiconductor device has a first group containing a predetermined number of the bridge patterns spaced at a first interval and a second group containing a predetermined number of the bridge patterns spaced at the first interval, the second group being located at a second interval from the first group. The second interval is larger than the first interval.

Semiconductor device and layout design system

To provide an electrophotographic photoreceptor excellent in electric characteristics and various characteristics, capable of forming a uniform photosensitive layer and excellent in repetitive characteristics, an image forming apparatus using it and an electrophotgraphic cartridge. A lamination type electrophotographic photoreceptor comprising an electroconductive substrate and a photosensitive layer formed thereon, characterized in that the photosensitive layer contains a compound represented by the following formula (1), the ratio of the weight of the compound represented by the formula (1) to the weight content of all binder resins contained in the photosensitive layer is from 0.15 to 0.6, and the weight of the compound represented by the formula (1) is maximum among all charge transport materials: wherein each of Ar, Arand Aris an aryl group which may have a substituent, each of Arand Arwhich are independent of each other, is an arylene group which may have a substituent, and each of nand nwhich are independent of each other, is an integer of from 1 to 3.

Electrophotographic photosensitive body, image-forming device using same and cartridge

To provide an electrophotographic photoreceptor having a high sensitivity, a good balance of various electric properties such as chargeability and residual potential, a good stability of the coating solution, and an excellent light resistance. An electrophotographic photoreceptor comprising an electroconductive support having thereon a photosensitive layer, wherein the photosensitive layer contains a compound represented by the following formula (1): (wherein Rrepresents a group having a chiral center, Rrepresents a hydrogen atom, an alkyl group which may have a substituent, or an aryl group which may have a substituent, Rand Reach independently represents an alkylene group which may have a substituent, or an arylene group which may have a substituent, and R, R, Rand Reach independently represents an alkyl group which may have a substituent, or an aryl group which may have a substituent, and at least one member of Rto Ris an aryl group having a substituent).

Electrophotographic photoreceptor and image-forming apparatus

An intermediate filmin a three-layered resist filmis formed by the chemical vapor deposition process at a temperature not higher than 300&#xb0; C., using Si(OR)(OR)(OR)(OR), where each of R, R, Rand Rindependently represents a carbon-containing group or a hydrogen atom, excluding the case where all of Rto Rare hydrogen atoms.

Method of fabricating a semiconductor device

A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.

Method of manufacturing semiconductor device

To realize an electrophotographic photoreceptor excellent in abrasion resistance, the photosensitive layer of the photoreceptor comprises a polyester resin containing a repeating structural unit represented by the formula (1) and a hydrazone compound. (In the formula (1), Arto Areach represents, independently of each other, an arylene group which may have a substituent. Xrepresents a bivalent group (including a single bond) and Xrepresents a bivalent group (including a single bond) with 3 or less atoms.)

Electrophotographic photoreceptor, and image forming device and electrophotographic photoreceptor cartridge using the same member cartridge

Growing community of inventors

Kanagawa, Japan

Masayuki Hiroi