Texas Instruments Corporation

Hitachi, Ltd.

Other

Masayuki Hira

Shunichi Sukegawa

Tsutomu Takahashi

Shinji Bessho

Yasushi Takahashi

Koji Arai

Takahiro Matsuzawa

Kouji Arai

Tsugio Takahashi

Yoritaka Saitoh

Yukihide Suzuki

Chisa Makimura

Hiroyuki Fujiwara

Keisuke Takeo

Atsuya Tanaka

Yasushi Ichimura

Kohji Arai

A plurality of sub word lines each have a length equivalent to the division of a main word line along the extension direction thereof, arranged along a bit line crossing said main word line, and are connected with a plurality of memory cells. A first sub word select line arranged in parallel to the main word line is extended to a plurality of sub arrays arranged in the extension direction of the word line. A second sub word select line is connected to the corresponding one of said first sub word select line to be extended orthogonally to a word line driving circuit area of an adjacent sub array. In the sub word line driving circuit provided for each sub array, a sub word line is selected and deselected by signals supplied from said main word line and said second sub word select line.

Dynamic RAM

The objective of this invention is to provide a static memory cell and an SRAM device that can improve the write margin while preventing degradation of the static noise margin. By turning on/off transistor Qpit is possible to control the drop in voltage due to the threshold voltage of transistor QnFor example, in read mode, when it is necessary to hold the stored data while setting word line WL to the high level, transistor Qpis turned off; the drivability of transistor pair QnQnis decreased, thereby increasing the static margin. In the case of rewriting the stored data, transistor Qpis turned on; the drivability of transistor pair Qn, Qnis increased, thereby increasing the write margin. As a result, it is possible to improve the performance of both the static noise margin and the write margin.

Static memory cell and SRAM device

This invention provides a type of sense amplifier, a type of bit line circuit, a type of storage device, and a method for amplifying a read signal characterized by the fact that it has a small detection error of the read signal and has low power consumption. With bit lines (BL, BLZ) and input terminals (SA, SAZ) of the amplifier connected to each other by means of a CMOS switch circuit, as control signal ENN becomes high level, amplification of the read signal in the amplifier starts and, at the same time, the amplified signal is held. After a time delay determined by delay circuit Ufrom the start of amplification of the read signal, control signal GENand control signal GENoutput from said delay circuit Uare changed, and connection between the bit line and amplifier is cut off. Consequently, while the small potential difference at the start of amplification is kept by the current from the bit line, the amplification operation is carried out to a certain degree, and then the bit line is cut off from the amplifier. Consequently, a detection error in the read signal can hardly take place.

Sense amplifier with reduced detection error

The semiconductor memory device has a memory capacity that can be increased without increasing the load to bit lines and has increased access speed. Because the output lines of bit line selector circuits through are precharged by charge circuits through , and selectable bit lines (SBL, SBLZ) reach a high level before access is gained for reading from memory cells, data read previously is held unchanged for output signal SAOUT of data latch circuit . Because output lines of bit line selector circuits through are all at the high level even when another gate circuit becomes conductive as a new read address is set, the selected bit lines remains at the high level, and data previously read is held unchanged for output signal SAOUT of data latch circuit . Output signal SAOUT of data latch circuit is changed to the next data read as soon as differential amplification operation of the bit lines is completed by amplifier circuits through

Semiconductor memory device

Drop in the power supply level right after change can be suppressed greatly when changing the power to the internal power supply voltage from the external power supply voltage of an overdrive system. Voltage generating circuit VG,is connected to the V,line which raises the V,line to a voltage higher than V,beforehand prior to changing to internal power supply voltage V,from external power supply voltage V,, and restores the V,line voltage which drops after the change to V,. More specifically, there are detecting circuit part,which detects the V,line potential, first switching element M,connected between the V,line and the V,line and which operates according to the detected result of detecting circuit part,, and second switching element M,connected between common voltage V,and connection node ND,between first switching element M,and detecting circuit part,, which changes the potential of connection node ND,by conducting according to input preliminary voltage step up signal MVDL, and by it conducts first switching element M,for a fixed time.

Voltage generating circuit for semiconductor memory sense amplifier

An equalizer control line BLEQ shared by all sense amplifiers SA in each row in each submat SM is connected to a first equalizer control line driver consisting of P-type MOS transistors installed at the left end of the submat SM and is connected to several second equalizer control line drivers 32 consisting of N-type MOS transistors installed by dividing in a cross area 16 of each row through which the equalizer control line BLEQ passes. In order to turn on the equalizers of the bit line pair connected to each sense amplifier S, the first equalizer control line driver is operated to drive the equalizer control line BLEQ to the H level potential. In order to turn off the equalizers of each bit line pair, the second equalizer control line drivers 32 are operated to drive the equalizer control line BLEQ to the L level potential. The first and second equalizer control line drivers are complementarily operated. One of them is driven, and the other is turned off (blocked).

Semiconductor memory device having plurality of equalizer control line

To reduce both the noise level according to separation or short-circuitng of the electrical supply line of the sense amplifiers and the electrical supply line of the word line driving circuit and to effectively prevent destruction of the stored data in the nonselecteded memory cell. Electrical supply line (Vssw) of the power supply voltage with respect to word line driving circuit (SWD) and electrical supply line (Vssa) of power supply voltage with respect to sense amplifier driving circuit (SAD) are arranged separately in memory array area 2 (e.g., in the space in the row direction of memory array (SMAx,y)) and connected to shared electrical supply wiring (Vsso) within peripheral circuit area 3.

Shared electrical supply line for a semiconductor storage device

The objective is to realize a semiconductor memory capable of avoiding an increase in the load of the sense amplifiers, easily realizing a large capacity and high integration of the memory, reducing the current consumption by the bit lines, and improving the access speed. Because the levels of the selection signal lines SHUS1, SHUE1, SHDS1, and SHDE1 are set by the control circuit, only one of the aforementioned four selection signal lines is selected at the time of memory access, other selection signal lines are held in unselect status, and the sense amplifiers in the sense amplifier bank SB1a and prescribed bit line pairs or extended bit line pairs are connected to each other by response in order to carry out read or write; thus, the load of the sense amplifiers can be reduced, and high speed, large capacity, and high integration can be achieved.

Semiconductor memory

Described herein is a dynamic memory. An N channel type voltage clamp MOSFET is provided which has a drain supplied with a supply voltage supplied from an external terminal, a gate to which a boosted constant voltage is applied, and a source which outputs a constant voltage. The clamp voltage outputted from the source of the voltage clamp MOSFET is supplied to a common source line for each of P channel type amplification MOSFETs constituting a sense amplifier via a P channel type first power MOSFET switch-controlled by a sense amplifier activation signal, as a voltage for operating the sense amplifier. Further, the constant voltage outputted from the source of the voltage clamp MOSFET is supplied to an N-well region in which the P channel type first power MOSFET and the P channel type MOSFETs constituting the sense amplifier are formed, as a bias voltage.

Dynamic memory

Realizing a reduction of the layout surface area by rendering unnecessary the region used for well isolation. In this DRAM, a triple well construction is used, and all of the regions for the unit memory cell array MA, the word line driver bank WDB, the sense amplifier bank SAB, and the cross area CR are surrounded by a lower layer N-type deep (deep layer) well 12. A back bias VPP corresponding to the power supply voltage of the word line driver is applied to the N well 14, and a back bias VBB corresponding to the characteristics of the memory cell are applied to the P well 16. In the N well 14, in regard to the P-type MOS transistors of the sense amplifier that undergo the substrate bias effect due to the back bias VPP, the threshold voltage is set to a low value so as to cancel that bias effect. Also, in the P well 16, in regard to the N-type MOS transistors of the sense amplifiers that undergo the substrate bias effect due to the back bias VBB, the threshold voltage is designed to a low value so as to cancel that bias effect.

Overall VPP well form

Controlling the timing for the overdrive of the sense amplifiers in response to the wiring length between the sense amplifiers and the power supply voltage supply nodes, and designing a reduction of the power consumption by preventing excessive overdrive of the bit lines. The supply timing for the power supply voltage to each sense amplifier bank is controlled according to the wiring length between the supply nodes CT0, CT1, CT2 for the power supply used for the driving of the sense amplifiers and each sense amplifier bank SB0 to SB16, and since the supply time for the overdrive voltage to the sense amplifier bank SB0 at the near end is set short and the supply time for the overdrive voltage is set successively longer as it goes towards the far end, the sensing delay that originates in the voltage drop that is generated in the wiring between the supply nodes and the sense amplifier banks is compensated for, uniformity of the overdrive for the bit lines at both the far and near ends can be achieved, the excessive overdrive at the sense amplifier bank (memory cell mat) at the near end can be avoided, and by extension, a reduction of the power consumption can be realized.

A semiconductor storage device is provided with a storage circuit for a faulty address and a plurality of redundant word lines corresponding to the storage circuit. The storage circuit is adapted to store a faulty address required for selecting a redundant word line. The faulty address is compared with an address input at the time of memory access by a comparator. Using a coincidence signal produced from the comparator and a predetermined address signal contained in the input address, a defect relief circuit selects one of the redundant word lines in place of the faulty word line.

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Ibaraki, Japan

Masayuki Hira