Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Masayuki Hata

Akira Yamada

Hiromasa Nakagawa

Toshiyuki Hiraki

Hiromi Maeda

Tatsuo Yamada

Itsuko Ishida

Katsunori Suzuki

Koichi Nishida

Yukihiko Shimazu

Tsunenori Umeki

Mitsugu Satou

Itsuko Kinoshita

A data processing unit includes a first power supply consisting of a stable power supply, a central unit operating on the firsts power supply, a second power supply, a peripheral unit operating on the second power supply, an interface block for transferring an external signal to the peripheral unit, and a power-down detector operating on the first power supply and connected to the second power supply, for detecting a power down of the second power supply and for generating a signal informing of the power down when it occurs. This power down signal can prevent supply of the external input signal to the central unit. The data processing unit solves problems of conventional data processing units including separate central unit and peripheral power supplies in that an unexpected power down of the peripheral use power supply can cause malfunctions of the central unit because of, e.g., an undesired interrupt signal.

Data processing unit including central unit and peripheral unit driven by separate power supplies

A data processing unit capable of solving a conventional problem in that a CPU cannot acquire the right of using a bus as long as a DMAC (Direct Memory Access Controller) has that right, and hence the operating ratio of the CPU reduces. A CPU bus is kept disconnected from the DMAC bus as long as the CPU disables the access request to a memory connected to the DMAC bus, and is connected to a DMAC bus in response to the access request unless the DMAC has the right of using a DMAC bus.

System for selectively connecting CPU bus to DMAC bus when accessing

A cache memory operates in a first mode, in which a cache hit occurs, and in a second mode, in which a cache miss occurs. A data processor operates in a first state in which instructions are accessed from memory and in a second state in which data is accessed from memory. Cache memory has a condition setting circuit which distinguishes instruction caching from a data caching. The processor sends an access-type signal which is compared with the access-type set in the condition setting circuit. When the access-type signal does not coincide with the contents of the condition setting circuit, a third state is declared which links the main memory and cache memory.

Cache system with access mode determination for prioritizing accesses to

A clock synchronous information receiving apparatus comprising a control signal circuit 6 for receiving a communication clock 3 and outputting a control signal 8, a control signal generating circuit 10 for outputting three control signals 121, 122, 123 differing in the timing of changing from high level to low level in synchronism with the communication clock 3, a communication data compensation circuit 11 for storing communication data 5 at the falling timing of the three control signals 121, 122, 123 of the control signal generating circuit 10, and determining the value of the communication data 5 from the stored values and sending out compensated communication data 50, and a serial/parallel converting circuit 7 for converting the compensated communication data 50 outputted serially from the communication data compensation circuit 11 into parallel and outputting into an 8-bit bus 9, thereby capable of receiving data correctly when noise is generated on the communication data.

Clock synchronous serial information receiving apparatus receiving

A cache memory apparatus allocates memory regions on the basis of information attributes. The required memory region corresponding to the attribute is accessed before caching is implemented. This enables considerable reduction in apparatus that would otherwise be required to be duplicated among different chips corresponding to the number of information attributes. In a multiple data processing implementation, cache memory regions are allocated for each data processor. The required memory regions of the cache memory are accessed in accordance with information specifying the data processor before caching is carried out. To avoid data collision when the main memory data is substantially rewritten, and when data having the same address and different access types exist simultaneously, data representing the type of access is stored. In response to a change in access, all data signals stored in each ways is nullified so that a plurality of data stored in the memory regions is not simultaneously output.

Memory apparatus and method capable of setting attribute of information

A data processor and method for preventing access to a cache memory when an abnormality occurs during a block data transfer. The data processor is provided with a central processing unit (CPU), a memory and the cache which stores a part of the data being stored in the memory. When the data to be accessed by the central processing unit is not stored in the cache, the data processor employs a block transfer method where the central processing unit reads out from the memory a block of data, including a predetermined number of data (words) in which the data to be accessed is located. When an abnormality, such as a parity error, is detected in transferring a data word in the block of data to be accessed, the cache is inhibited from reading another data word in the block to be accessed, and the CPU stops reading out the rest of the block of data to be read out from the memory, so that the central processing unit can immediately take action to respond to the abnormality.

Data access apparatus for preventing further cache access in case of an

A computer system is provided with a plurality of cache memories. Each cache memory stores data corresponding to part of main memory address space without overlapping with each other, thereby enabling capacity of the cache memory to be increased with ease. An address mask register is used to allocate the portion of main memory address space stored in each cache.

Computer system with cache memory having address mask register

An associative memory comprises a CAM array which is divided into a plurality of blocks, block select means, decoder means, and output means. The associative memory receives an externally supplied input address having first, second, and third parts. Which entry row in the CAM should be compared with the first part (TAG address) of the input address is determined by the second and third parts of the input address. The block select means responsive to the second part of the input address selects a block in the CAM. The decoder means responsive to the third part of the input address selects one out of a plurality of entry rows in the selected block. A comparison operation is carried out in each of the entry rows in the selected block. Since not all the entry rows are selected for comparison operations, power consumption can be reduced.

Associative memory

A clock synchronous serial information transfer apparatus, comprises, a control signal circuit 6 which inputs a clock CLKin, and judges that the same level has continued over a predetermined time to output the judging result as two complementary control signals CLKa and CLKb, latch circuits 9a to 16a operated by a control signal which outputs a high level when the clock CLKin inputted to the control signal circuit 6 has kept the high level, and latch circuits 9b to 16b operated by a control signal which outputs the high level when the clock CLKin inputted to the control signal circuit 6 has kept a low level, whereby data is transmitted and received correctly even when noises occur in the clock CLKin.

Clock synchronous serial information transfer apparatus

A data processor which accesses a memory system only by a block transfer mode for transferring multiple data from the memory system when a cache misses a CPU read-access request for a single data. The data of the address designated by the CPU is read simultaneously into the CPU and cache in parallel from the memory system. After the CPU completes this read-access, the cache is then adapted to continue to read the rest of the multiple data transferred in the block transfer mode. During this time, the CPU does not newly assert an address signal, a bus control signal, and the like but continues to execute its internal processing, such as pipeline processing.

Cache bypass system with simultaneous initial transfer of target data to

A clock generator which is provided with a circuit generating non-overlap clock from input clock, a frequency dividing circuit driven by the non-overlap clock and a latch disposed between the frequency dividing circuit and a clock driver, and whose critical pass being a cause of delay is shortened by sampling the frequency-divided output into the latch by the input clock and thereafter driving it by the clock driver, and a clock generator in which an internal clock at high speed in the internal clock logical value generating circuit is added with internal clock edge generating circuit required to operate at high speed and an output of initial stage of a buffer for inputting external clock is divided to supply to the internal clock edge generating circuit and to the other circuits, thereby capacity of the buffer required to operate at high speed in the circuit is decreased to reduce the delay of external clock.

Stable high speed clock generator

For performing the coincidence detection between data stored in a memory and comparison data supplied from an external at a high speed, the positive data of a memory 1a is transmitted to a positive sense amplifier 2-1, the negative data is transmitted to a negative sense amplifier, and comparison data 5 and the inverted data thereof are respectively inputted as activating signals of the positive and negative sense amplifiers to an activating circuit. Due to the comparison data, the output of the non-activated sense amplifier always becomes 'H'. On the other hand, the activated sense amplifier senses and outputs its input potential. The output signals of these sense amplifiers are inputted to a coincidence signal outputting circuit to determine a coincidence signal.

Memory circuit with dual sense amplifier and amplifier control circuitry

A control method for a data processing circuit which controls the timing of two clocks which independently control data latch circuits connected respectively with an input side and an output side of a logic circuit. The two clocks are held at a level which allows both data latch circuits to sample an input signal for a predetermined period. A data latch circuit comprises a first gate controlling whether or not an input signal is conducted to the logic circuit, an input end of a buffer circuit for latching the data signal and an output end of a second gate which causes an output of the buffer circuit to pass to an output end of the first gate, and a data processing circuit capable of sampling data, logically processing it, latching the result of the processing, and outputting it in one clock cycle, by interposing a logic circuit between the aforementioned two data latch circuits.

Method and apparatus for latching data around a logical data processor

In a data processor, when there is any cache memory not being activated after the whole data processor has been activated, a signal is delivered to a bus driver and then a data processing unit is connected to a system bus. During the period from when the whole data processor has been activated to when all the cache memories start to be activated, the data processing unit is connected to the system bus so that data can be transmitted/received between the data processing unit and peripheral devices.

Plural cache architecture for real time multitasking

A least-recently-used (LRU) circuit determines a replaceable term needed for storing data newly loaded from cache memory for example. The circuit comprises a recently-used information storing means relating to the top priority order or the subordinative order among plural terms, and a least-recently-used determining means for determining which is the top priority term or the subordinative term in accordance with information stored in the recently-used information storing means. High speed processing is thus possible by simplified logical construction. Also, the circuit is provided with control means which directly or indirectly select the predetermined replaceable term, in situations where the determining means cannot properly determine the top-priority replaceable term. Therefore, even when the top-priority replaceable term is selected directly or indirectly, the cache memory can be securely prevented from discontinuing its own functional operation.

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Itami, Japan

Masayuki Hata