Nec Corporation

Renesas Electronics Corporation

Nec Electronics Corporation

Matsushita Electric Industrial Co., Ltd.

Masayuki Hamada

Ken Inoue

Takeshi Watanabe

Mitsunari Sukekawa

Akira Hoshino

Takehiko Hamada

Tsuyoshi Okada

Hisashi Kurokawa

A semiconductor device includes a semiconductor substrate including a DRAM portion and a logic portion thereon, an interlayer film covering the DRAM portion and logic portion of the semiconductor substrate, and plural contact plugs formed in the interlayer film in the DRAM portion and the logic portion, the plural contact plugs being in contact with a metal suicide layer on a highly-doped region of source and drain regions of first, second and third transistors in the DRAM portion and the logic portion, an interface between the plural contact plugs and the metal silicide layer being formed at a main surface in the DRAM portion and the logic portion.

Semiconductor device and manufacturing method thereof

In a DRAM-incorporated semiconductor device (SOC) which has a DRAM section and a logic section being formed on one and the same substrate, with the object of providing, with low cost, a SOC having necessary and sufficient characteristics in the DRAM section, while attaining higher-speed performance of the whole elements, silicide is formed at least on all the surfaces of the source-drain regions () and the gate surfaces () of transistors in the DRAM section and the logic section, concurrently in one and the same step.

Semiconductor device having a memory cell section, an adjacent circuit section, and silicide formed on an impurity diffused region

Dynamic random access memory with silicide contacts, CMOS logic section and LDD structure

A semiconductor device includes: a first sense amplifier; a first bit line coupled to the first sense amplifier; a second bit line disposed next to the first bit line and electrically coupled to a constant-voltage source; and a first reference cell, including: a first transistor having a source and a drain, one of which is coupled to the first bit line; a second transistor, having a source and a drain, one of which is coupled to the second bit line, and the other coupled to the other of the source and drain of the first transistor, which is not coupled to the bit line BL; and a capacitance Chaving electrodes, one of which is coupled to the other of the source and the drain of the first transistor, and the other of the source and the drain of Tr

Semiconductor device

In a DRAM-incorporated semiconductor device (SOC) which has a DRAM section and a logic section being formed on one and the same substrate, with the object of providing, with low cost, a SOC having necessary and sufficient characteristics in the DRAM section, while attaining higher-speed performance of the whole elements, silicide is formed at least on all the surfaces of the source-drain regions ( ) and the gate surfaces ( ) of transistors in the DRAM section and the logic section, concurrently in one and the same step.

Method of manufacturing a semiconductor device having a memory cell section and an adjacent circuit section

A semiconductor memory device includes a capacitive insulating film and an upper electrode formed at the inner surface of the cylindrical lower electrode to form a capacitive cell. Near the capacitive cell, a groove with the same depth as that of the capacitive cell is formed and electric conductive layers are formed at the inner surface thereof. The electric conductive layer and upper electrode are connected by the upper electrode extending part. At the bottom of the groove, the upper electrode contact is connected to the electric conductive layer.

Semiconductor memory device and manufacturing method and mask data preparing method for the same

The present invention provides a method of selectively forming a silicide layer on a logic region of a semiconductor substrate which has an integration of a memory cell region and the logic region. The method comprises the steps of: forming an insulation film over the memory cell region and the logic region; entirely applying a resist film over the insulation film; selectively removing the resist film over at least a predetermined part of the logic region by use of a lithography process, whereby the insulation film is shown over the logic region; selectively etching the insulation film over the logic region by use of the resist film, whereby at least a silicon region is shown over the logic region; removing the resist film; entirely depositing a refractory metal layer on the insulation film over the memory cell region and also on the silicon region over the logic region; carrying out a heat treatment to cause a silicidation reaction to form at least a silicide layer on the silicon region over the logic region; and removing an unreacted refractory metal layer from the silicon oxide film.

Method of selectively forming a silicide layer on a logic area of a semiconductor substrate

A method of manufacturing a semiconductor device, in which a contact alignment mark ( A) is formed in an interlayer insulating film ( ), and a wiring alignment mark ( A) is formed above a gate alignment mark ( A) so that the size of the wiring alignment mark ( A) is slightly larger than the gate alignment mark ( A). At the same time, all the other alignment marks at the lower side are shielded by a shield film ( S). Opaque alignment mark and opaque shield film are formed to shield all the alignment marks at the lower side, whereby the alignment marks can be successively formed while stacked on one another.

Semiconductor substrate and method of manufacturing semiconductor device

A semiconductor device is manufactured in accordance with the following steps. A prospective lower interconnection layer is formed on a substrate, and is patterned to form a lower interconnection. A first nitride film is formed on the entire surface. A first interlevel insulating film is formed on the entire surface of the first nitride film. A prospective upper interconnection layer is formed on the first interlevel insulating film, and is patterned to form an upper interconnection. A second nitride film is formed on the entire surface. The second nitride film is removed by patterning where a contact reaching the lower interconnection is to be formed. A second interlevel insulating film is formed on the entire surface. A plurality of contact holes are formed simultaneously to have different depths and reach the first and second nitride films respectively formed on the lower and upper interconnections. The first and second nitride films located at bottoms of the contact holes are etched simultaneously to form a plurality of contact holes which have different depths and reach the lower and upper interconnections, simultaneously.

Method of manufacturing semiconductor device having contacts with different depths

A contact alignment mark (18A) is provided in an interlayer insulating film (17), and a wiring alignment mark (19A) is formed above a gate alignment mark (15A) so that the size of the wiring alignment mark (19A) is slightly larger than the gate alignment mark (15A). At the same time, all the other alignment marks at the lower side are shielded by a shield film (19S). All the alignment marks at the lower side are shielded by the opaque alignment mark and the opaque shield film, whereby the alignment marks can be successively formed while stacked on one another.

To cancel an error in GPS wave propagation time and calculate a relative position of a car running nearby to the own car position with good accuracy, a relative car positioning system using car communication includes a car communication transceiver, a GPS receiving device, a GPS information transmission/reception device, and a relative positioning device. A relative position is determined by determining a GPS wave propagation time difference from a GPS satellite, a wave of which is received by the car running nearby and the own car in common. The difference between the data of GPS wave propagation time at the car running nearby and the data of GPS wave propagation time at the own car is calculated, and if the number of differences of the GPS wave propagation time is obtained by more than three pieces, a relative position of the car running nearby is calculated by solving simultaneous equations expression the relative position as an unknown quantity.

Relative car positioning system using car communication

A method of fabricating a semiconductor device, including the steps of (a) forming a channel at a surface of a semiconductor substrate only in the center of a region X which physically and electrically isolates adjacent regions Y in each of which a device is to be fabricated, and (b) forming a silicon oxide layer over the region X for physically and electrically isolating the adjacent regions Y from each other. The method suppresses dimensional shift and occurrence of a stress, and further makes it difficult for the reverse narrow channel effect to occur only by adding the small number of additional steps thereto.

Growing community of inventors

Tokyo, Japan

Masayuki Hamada