Hitachi, Ltd.

Masayoshi Yoshimura

Masahiro Iwamura

Ikuro Masuda

Yukio Suzuki

Toshiaki Matsubara

Shinji Kadono

Akira Uragami

Takashi Yamaguchi

Ichiro Imaizumi

Masatoshi Kimura

Shikayuki Ochi

Toyomasa Koda

Ichio Shimizu

Tomio Yamada

Keizo Otsuki

Yuji Arai

Senji Shoji

Akiro Uragami

Akira Urragami

In an input level converter for TTL--CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS--TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.

BiCMOS tri-state output driver

Level conversion circuitry for a semiconductor integrated circuit

In an input level converter for TTL-CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS-TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.

In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS - TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.

Semiconductor integrated circuit with a bi-MOS input circuit for

Bicmos gate array

A high-breakdown-voltage semiconductor device wherein a resistor body made of a P-type impurity region is disposed in a surface region of an N-type semiconductor body so as to form a resistor element, a P-type low doped region is disposed around the resistor body, and a plate layer which extends from a high potential electrode of the resistor body covers a main part of the P-type low doped region.

High-breakdown-voltage semiconductor device

A high-breakdown-voltage resistance element comprises a semiconductor body, an impurity layer disposed in a surface region of the semiconductor body to provide a resistor body, a first electrode connected to one end of the resistor body through a contact hole in a first insulating film formed on the surface of the semiconductor body, and a second electrode connected to the other end of the resistor body through another contact hole in the insulating film. A second insulating film is formed on the first and second electrodes, and a third electrode is connected to the first electrode through a contact hole in the second insulating film, so that the entire surface of the resistor body and adjacent areas are covered with the first, second and third electrodes.

High-breakdown-voltage resistance element for integrated circuit with a

A single in-line, high power, resin-packaged semiconductor device having a plurality of external leads disposed in parallel to each other and projecting from one side surface of a resin-molded package, wherein a heat sink fin mounting plate is formed in unitary structure with a plate for carrying a semiconductor pellet and arranged to project from a recessed portion of the opposite side surface of the resin-molded package and a heat sink fin has one end bent in U-shape and caulked on the fin mounting plate and the remaining portion overlapping one principal surface of the resin-molded package. The projection of the heat sink fin from the resin-molded package can be reduced to enable the device to be assembled in compact electronic instruments or devices. Heat dissipation efficiency can also be improved by mounting the semiconductor device on a chassis with the heat sink fin brought in contact with the chassis.

Single in-line high power resin-packaged semiconductor device having an

An epitaxial silicon layer is grown on a principal surface of the (100) crystal face of a silicon single crystal having a depressed portion in the principal surface. The epitaxial silicon layer is flattened by etching, the epitaxial silicon layer being formed to a sufficient thickness so that the side surfaces of the crystal face (111) of a new depressed portion as viewed in a vertical section (the new depressed portion being formed in a surface of the epitaxial silicon layer in correspondence with the first-mentioned depressed portion) intersect at a level which is, at the lowest, the final plane of the etching. The etching is anisotropic etching with an alkali etchant, by which the epitaxial silicon layer is etched down to the final plane.

Etching method for flattening a silicon substrate utilizing an

In a transistor wherein a second conductivity type region is formed surrounding a first conductivity type region in a principal surface electrodes are formed on a surface of the first conductivity type region, an electrode of the second conductivity type region is formed in a manner to encircle the first-mentioned electrodes, and electrodes of the first conductivity type region are led outside the electrode of the second conductivity type region through an insulating film, whereby concentration of current is prevented.

Transistor with base/emitter encirclement configuration

A transistor circuit which comprises a first transistor of the N-P-N type, a second transistor of the P-N-P type and a third transistor of the N-P-N type, and in which a base of the first transistor, an emitter of the second transistor and a collector of the third transistor are electrically connected with one another, while a collector of the first transistor and a base of the second transistor are electrically connected with each other, whereby the first transistor is prevented from being driven into an extremely deep saturation region.

Transistor circuit for deep saturation prevention

A semiconductor integrated circuit contains a resistance element, wherein a low resistance region of a first conductivity type, employed for a circuit resistance, is formed within a high resistance region of a second conductivity type, opposite to the first conductivity type. The low resistance region and the high resistance region are connected in parallel, so as to prevent the formation of a parasitic transistor and a parasitic thyristor.

Growing community of inventors

Maebashi, Japan

Masayoshi Yoshimura