Hitachi, Ltd.

Renesas Electronics Corporation

Masayoshi Yagyu

Hiroki Yamashita

Tatsuya Saito

Norio Chujo

Noboru Masuda

Fumio Yuuki

Tatsuya Kawashimo

Yutaka Uematsu

Hiroyuki Itoh

Akira Masaki

Minoru Yamada

Mitsuo Asai

Moritoshi Yasunaga

Mitsuo Usami

Takeshi Kato

Toshio Yamada

Shuuichi Kariyazaki

Kazuyuki Nakagawa

Masakazu Yamamoto

Takashi Takemoto

Keita Tsuchiya

Katsunari Shibata

Yoshiaki Sato

Katsuya Tanaka

Takehisa Hayashi

Hiroki Ikeda

Takashige Baba

Kenichi Ishibashi

Tohru Kobayashi

Tetsuya Uemura

Toshio Doi

Masato Hamamoto

Koji Fukuda

Jun Sugawa

Hisaaki Kanai

Masahide Tokuda

Ryotaro Kamikawai

Yuuji Fujita

Yosuke Katsura

Shigeo Oomae

Tsuneyo Chiba

Shinji Katayama

Tomohisa Iwanaga

Yuzo Hirai

Hiroyuki Itho

Masaru Osanai

In a multilayer wiring board having through holes used in an electronic device, wiring is efficiently performed at high density while preventing crosstalk of differential signals. A wiring board includes: a plurality of pads arranged linearly at a predetermined pitch; a plurality of through holes arranged in parallel along an arrangement direction of the pads; and a wiring pattern connecting the pad to the through hole. Between the through holes connected to the pads which are connected to the ground via the wiring patterns, two through holes through which each of a pair of differential signals constituting a differential signal pair passes are provided such that a direction of a straight line connecting the two through holes is inclined to the arrangement direction of the pads.

Wiring board and electronic device

Performance of a semiconductor device is improved. The semiconductor device includes a semiconductor chip and a chip component that are electrically connected to each other via a wiring substrate. The semiconductor chip includes an input/output circuit and an electrode pad electrically connected to the input/output circuit and transmitting the signal. The chip component includes a plurality of types of passive elements and includes an equalizer circuit for correcting signal waveforms of the signal, and electrodes electrically connected to the equalizer circuit. The path length from the signal electrode of the semiconductor chip to the electrode of the chip component is 1/16 or more and 3.5/16 or less with respect to the wavelength of the signal.

Semiconductor device

A semiconductor device includes a semiconductor chip mounted over a wiring substrate. A signal wiring for input for transmitting input signals to the semiconductor chip and a signal wiring for output for transmitting output signals from the semiconductor chip are placed in different wiring layers in the wiring substrate and overlap with each other. In the direction of thickness of the wiring substrate, each of the signal wirings is sandwiched between conductor planes supplied with reference potential. In the front surface of the semiconductor chip, a signal electrode for input and a signal electrode for output are disposed in different rows. In cases where the signal wiring for output is located in a layer higher than the signal wiring for input in the wiring substrate, the signal electrode for output is placed in a row closer to the outer edge of the front surface than the signal electrode for input.

A low offset input circuit and a signal transmission system which can accommodate a high-speed interface and achieve reduction of an offset voltage are provided. An offset voltage compensating circuit blockhaving an input circuit blockincluding an input circuitand an adder-subtractor circuit block, switches, a detecting circuit block, and an adjusting and holding circuit blockis provided. To compensate for an offset voltage of the input circuit block, an offset voltage of the input circuit blockis detected at the detecting circuit blockby turning on the switches, and the detected offset voltage is held in the adjusting and holding circuit block, and negative feedback of the held offset voltage to the adder-subtractor circuit blockis performed. Thereby, signals Vop, Von having compensated offset voltages are outputted from the input circuit block

Low offset input circuit and transmission system with the input circuit

A burst mode receiver including a CDR circuit that does not perform bit synchronization determination at a wrong position even when a burst signal waveform containing a distortion is input is provided. The burst mode receiver includes a CDR circuit for reproducing clock and data from a received signal, a bit synchronization determination circuit for determining whether the CDR circuit is in an optimum phase, a waveform distortion determination circuit for determining from the received signal whether there is waveform distortion, and a CDR output enable determination circuit for determining whether an output of the CDR circuit is valid or invalid. The CDR output enable determination circuit performs CDR output enable determination based on a bit synchronization determination result and a waveform distortion determination result.

Burst mode receiver

In an adjustment method of waveform equalization coefficient, one of jitter and amplitude is measured only in a case of an arbitrary signal sequence and a waveform equalization coefficient is adjusted. Particularly, using a signal of received signals other than a 010 signal or a 101 signal, code inversion time is measured. Since the code inversion time in a case where such signals are used becomes steeper in comparison with that in the conventional technique, adjustment time of the waveform equalization coefficient can be reduced.

Adjustment method, circuit, receiver circuit and transmission equipment of waveform equalization coefficient

In a signal transmission system where an influence of the circuit characteristic variation of an input circuit on signal receiving operation cannot be ignored, there is provided a method of realizing a low-offset input circuit which is capable of conducting high-speed operation and always continuing signal receiving operation without increasing the number of terminals of a semiconductor integrated circuit and without the necessity of providing additional signal observing means and variation adjustment amount calculating means to the external of the semiconductor integrated circuit. In a signal receiver circuit having an input circuit, an automatic zero amplifier, an analog/digital converter circuit, an encoder circuit, and a signal holding circuit, an output error signal of the input circuit is amplified by the automatic zero amplifier, and the signal is digitalized or the digitalized signal is encoded as the occasion demands, and held by the holding circuit, and the circuit characteristic variation of the input circuit is adjusted by the held signal.

Low-offset input circuit including amplifier circuit to correct circuit characteristics to cancel offset of the input circuit

For example, a gain control part and a common node control part are provided in a logic circuit including a data acquisition part that has a differential amplifier configuration and acquires a data input signal when a click signal is an 'H' level and a latch part that latches a data output signal from the data acquisition part when the click signal is an 'L' level. The gain control part is provided between common nodes of NMOS transistors in the differential amplifier and serves to make the gain of the differential amplifier higher in a high frequency band than in a low frequency band. When the clock signal is an &#x201c;L&#x201d; level, the common node control part serves to control an electrical charge so as to eliminate a potential difference between the common nodes. Thus, the transition time of the data output signal is speeded up and the setup margin is increased in the latch part. The above described technique can therefore speed up operations of various logic circuits such as a latch circuit.

Logic circuit

A magnetic recording device capable of reducing the size of a writing circuit and the power consumption by readily adjusting the overshoot of the write current pulses is provided. Two or more transmission lines having different characteristic impedances are provided between an output driver having an impedance Zand a magnetic head, the transmission lines are formed so that the characteristic impedances Z, Z, and Z(n&#x2267;2) thereof on the output driver side are higher than those on the magnetic recording head side (Z&#x3e;Z&#x3e;Z), and the impedance Zof the output driver is equal to or higher than the characteristic impedance Zof the transmission line.

Magnetic recording device

This invention provides a signal transmission circuit, a signal output circuit, and a termination method of a signal transmission circuit capable of preventing the re-reflection of the signal at a transmitting node of a transmission path even when an impedance of a signal output circuit does not match a characteristic impedance of a transmission path. On a signal transmission circuit composed of a transmission path, a signal output circuit connected to a transmitting node of the transmission path, and a signal receiver circuit connected to a receiving node of the signal transmission path, in order to prevent the re-reflection of an output signal of a signal output unit at the transmitting node via the receiving node, a correction current generator unit is provided for outputting correction current with a predetermined current amount and at a predetermined timing set in a current amount/timing control section, to the transmitting node.

Signal transmission circuit, signal output circuit and termination method of signal transmission circuit

This invention provides a semiconductor device in which an ESD protection circuit and a termination circuit can be realized with a small die area. A PMOS transistor having an ESD protection function is placed between a signal node on a line from an signal terminal to an input buffer and a supply voltage node. Furthermore, a voltage generator circuit is placed to supply a reference voltage to the gate of the PMOS transistor. By the reference voltage controlled by the voltage generator circuit, a source drain resistance of the PMOS transistor is set. Thereby, the PMOS transistor can be made to function as a terminating resistor whose resistance can be set adaptively to a characteristic impedance of a transmission line, for example, connected to the signal terminal in addition to the ESD protection function.

A signal communication apparatus of a clock reproduction system in which clock signals are extracted from each of parallel data signals for redigitizing each of the data signals. The apparatus includes a reference clock signal generating circuit which is comprised of a clock extraction circuit for extracting a clock signal from each of a plurality of bits of received data signals, and a clock signal selection circuit for selecting one of the extracted clock signals. Alternatively, the reference clock signal generating circuit may be comprised of a data signal selection circuit for selecting one of a plurality of received data signals, and a clock extraction circuit for extracting a clock signal from the selected bit. Based on the resultant reference clock signal, clock signals are obtained that are phase-adjusted for redigitizing each bit of the received data signals. The selection made in the selection circuit is switched on the basis of the output of a clock signal monitoring circuit that detects the occurrence of abnormalities in the frequency of the extracted clock signal. Thus, the extraction of clock can be continued using other bits in the event of an abnormality in the bit from which the clock is being extracted.

Clock extracting fabric in a communication device

The present invention provides a semiconductor integrated circuit capable of reducing a circuit area and a magnetic storage device using the same. The circuit in the present invention is provided with a single-stage output transistor for supplying write current to a magnetic head, a current source for outputting reference current of the write current, a diode-connected NMOS transistor for converting the current to gate voltage and having a certain device size ratio to the output transistor, a regulator circuit for transmitting gate voltage of the NMOS transistor and reducing output impedance, and a CMOS circuit for setting power supply voltage to an output of the regulator circuit and controlling the gate voltage of the output transistor. Then, this circuit is applied as a write circuit in a magnetic storage device.

Semiconductor integrated circuit and magnetic storage device using the same

A logic circuit determines the power consumption of a semiconductor integrated device by taking into consideration the variation of the rate of operation. A control signal (TEST) is applied to each control signal input port (Tin) of flip-flop circuits of flip-flop circuit groups and a logic gate circuit having a plurality of input ports A and B in a combined circuit group. If the control signal (TEST) is low, both the flip-flop circuits and the logic gate circuit operate normally. However, if the control signal (TEST) is high, each of them performs the power consumption test. Regardless of the value of input signals applied to input ports D1 and D2 of the flip-flop circuits, the flip-flop circuits are controlled to have a repetitive output signal of high and low levels at ports Q1 and Q2, in synchronism with a clock signal. Through this operation test, operational failure is reduced and the quality of semiconductor chip production is guaranteed, because it is possible to predict accurately the power consumption when designing the logic circuit due to the relationship between the rate of operation and the power consumption.

Method and circuit for determining the power consumption requirements for a semiconductor logic circuit and designing the circuit accordingly

A condenser having a huge area is required to reduce a noise on LSI power supply nets (&minus;&Dgr;VDD) of an integrated circuit because a bypass condenser can only utilize a part of accumulated electric charges. A noise of LSI power supply nets is suppressed by generating a noise of a reversed polarity (&plus;&Dgr;VDD) to the noise on the LSI power supply nets (&minus;&Dgr;VDD), based upon a noise reducing circuit discharging a condenser charged with a high voltage. A noise reduction effect equivalent to a bypass condenser having a large capacity is obtained even when a condenser having a small capacity is used.

Low noise integrated circuit device for reducing a noise on LSI power supply nets to supply electric charges required to operate IC

Growing community of inventors

Hanno, Japan

Masayoshi Yagyu