Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Masayoshi Toujima

Masatoshi Matsuo

Tomonori Yonezawa

Shunichi Kurohmaru

Masahiro Ohashi

Yasuo Kohashi

Koji Kai

Mana Hamada

Hitoshi Fujimoto

Yasuo Kouhashi

Takashi Hashimoto

Akihiko Inoue

Hiromasa Nakajima

Tomonori Kataoka

Misako Matsumoto

An integrated circuit including a shared memory connected to a bus, an audio/multiplex/de-multiplex processor accessing the shared memory via the bus, a video processor performing heavy processes accessing the shared memory via the bus, and a local memory accessed by the video processor without passing through the bus. The integrated circuit avoids a latency time caused by access contention, such that a probability that the integrated circuit can complete processes to be done in real time is increased. Image data is displayed on the display device smoothly without deterioration of quality of display.

Integrated circuit and electric device for avoiding latency time caused by  contention

In a data-sending device, a data generation section provides input data itself or a bit-inverted version of the input data as intermediate data and generates an inversion signal that indicates whether or not the intermediate data is the bit-inverted version of the input data. An encrypting section generates scrambled data by inserting the inversion signal in the intermediate data at a bit position. A data-receiving device removes the inversion signal from the scrambled data, and restores the input data based on the inversion signal.

Data transfer system

For every data, the number of data matches that occurred consecutively is written to a memory together with nonmatching data, and data from the memory is read out to continuously perform subsequent data processing and detect, at the same time, the last data written to the memory. To achieve this, a desired value is set in a data register, and a comparison instruction is issued by which the value set in the register is compared with a value set in a second register, and the number of matches that occurred consecutively is output together with nonmatching data; upon the output of a retrieval counter reaching a predetermined value, the comparison instruction is terminated, whereupon the number of consecutive matches, the nonmatching data, and an end flag signal are written to the memory at the same address.

Arithmetic unit and data processing unit

A conversion unit having a bidirectional conversion function of converting analog video signals into digital image data and vice versa and a processing unit having a function of encoding image data and of decoding encoded data are provided. A data transmission control unit switches the flow direction of each of image data and encoded data in response to an encoder/decoder switch signal. A process control unit performs switching of the receiving/transmitting of a control signal such as a transmission clock signal relating to encoded data in response to a master/slave set signal.

Image processor

A bus switch is connected among an input buffer memory, a data memory, and an encoding unit, to select between a first bus connection of the input buffer memory and the data memory and a second bus connection of the data memory and the encoding unit. A data transfer control unit controls the bus switch to select the first bus connection in response to a data request signal from the encoding unit, controls the process of reading from the input buffer memory and the process of writing into the data memory, controls the bus switch to select the second bus connection upon completion of the transfer of one unit of image data, and sends a transfer completion signal in order of causing the encoding unit to start performing encoding processing. This makes it possible to transfer image data from the input buffer memory to the data memory at high speed.

Image processor capable of transferring image data from an input buffer

Growing community of inventors

Kasuya-gun, Japan

Masayoshi Toujima