Mitsubishi Electric Corporation

Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Masayoshi Tarutani

Tsuyoshi Horikawa

Takaaki Kawahara

Mikio Yamamuka

Shigeru Matsuno

Takehiko Sato

Takeharu Kuroiwa

Yosuke Nakata

Ryu Kamibaba

Tetsuo Takahashi

Akira Yamada

Kenji Harada

Masayuki Imaizumi

Shinya Soneda

Kenichi Ohtsuka

Nobuyuki Tomita

Kenichi Hamano

Kazuhiko Sakutani

Masao Takata

Kouichi In

Akihiko Furukawa

Naruhisa Miura

Shiro Hino

Fusaoki Uchikawa

Yuji Abe

Hiroshi Takada

Atsushi Narazaki

Yosuke Takeuchi

Takashi Takenaga

Mikio Tsujiuchi

Kazuya Konishi

Sunao Aya

Yoichiro Mitani

Yuji Ebiike

Yasuhiro Yoshiura

Yukiyasu Nakao

Tomokatsu Watanabe

Takao Sawada

Hiroaki Sumitani

Takao Kachi

Seiya Nakano

Takuya Hamaguchi

Tomoaki Furusho

Yusuke Fukada

Mariko Umeyama

Kenji Ohtsu

Taku Kusunoki

Included are a semiconductor substrate, an emitter electrode formed on the semiconductor substrate, a gate electrode formed on the semiconductor substrate, a source layer of a first conductivity type formed on the semiconductor substrate, a base layer of a second conductivity type formed on the semiconductor substrate, a collector electrode formed under the semiconductor substrate, a plurality of active trench gates formed on a top-surface side of the semiconductor substrate and connected to the gate electrode, and a plurality of dummy trench gates formed on the top-surface side of the semiconductor substrate and not connected to the gate electrode. First structures, each including three or more of the active trench gates arranged side by side, and second structures, each including three or more of the dummy trench gates arranged side by side, are alternately provided.

Semiconductor device

There is provided a semiconductor device having a structure that can suppress occurrence of chipping in a device region and that can reduce manufacturing cost of the semiconductor device. A semiconductor device includes a substrate and a first amorphous insulating film. The substrate has a main surface and an end surface. The main surface includes a peripheral region and a device region. The first amorphous insulating film is disposed on the peripheral region, and is separated from the device region. The first amorphous insulating film extends along the end surface in the form of a stripe. The first amorphous insulating film is flush with the end surface.

An RC-IGBT includes a first electrode disposed on a first main surface of a semiconductor substrate over a transistor region and a diode region. The semiconductor substrate includes a MOS gate structure on a first main surface side in the transistor region. The RC-IGBT includes: an interlayer dielectric covering a gate electrode of the MOS gate structure, and having a contact hole exposing a semiconductor layer; and a barrier metal disposed in the contact hole. The first electrode enters the contact hole, is in contact with the semiconductor layer of the MOS gate structure through the barrier metal, and is in direct contact with a semiconductor layer in the diode region of the semiconductor substrate.

Semiconductor device, semiconductor device manufacturing method, and power conversion apparatus

An aluminum electrode () is provided on a semiconductor device (). A metallic film () for a solder joint is provided on the aluminum electrode (). The organic protective film () is apart from the metallic film (). An interval between the organic protective film () and the metallic film () is equal to or greater than half of a thickness of the organic protective film (). Thus, even when the organic protective film () is deformed during sinter joining, the stress is not transmitted to the metallic film (). Therefore, it is possible to prevent the solder connection metallic film () from cracking.

Semiconductor device and manufacturing method therefor

A semiconductor device of the present invention includes a semiconductor element, a surface electrode formed on a surface of the semiconductor element, a metal film formed on the surface electrode so as to have a joining portion and a stress relieving portion formed so as to border on and surround the joining portion, solder joined to the joining portion while avoiding the stress relieving portion, and an external electrode joined to the joining portion through the solder.

Semiconductor device and semiconductor device manufacturing method

According to a first aspect of the present invention, a method of manufacturing semiconductor device includes the step of preparing a silicon substrate. The silicon substrate includes an N-type silicon layer on one surface and at least one of a PN junction, an electrode film, and a protective film on another surface. The method includes the steps of forming a Si&#x2014;Ti junction by forming a first electrode film made of titanium on the N-type silicon layer; forming a second electrode film made of Al&#x2014;Si on the first electrode film; forming a third electrode film made of Ni on the second electrode film; and heating the silicon substrate after forming the third electrode film. A titanium silicide layer is not formed between the N-type silicon layer and the first electrode film.

Semiconductor device and method of manufacturing semiconductor device

The semiconductor element has an electrode including: a Ni-inclusion metal layer containing nickel formed on a side of at least one surface of the semiconductor-element constituting part; a Ni-barrier metal layer formed outwardly on a side of the Ni-inclusion metal layer opposite to the side toward the semiconductor-element constituting part; and a surface metal layer outwardly formed on a side of the Ni-barrier metal layer opposite to the side toward the semiconductor-element constituting part, to be connected to the metal nanoparticles sintered layer; wherein the Ni-barrier metal layer contains a metal for suppressing diffusion of nickel toward the surface metal layer.

Semiconductor element, semiconductor device and method for manufacturing semiconductor element

A semiconductor device capable of suppressing time variation of a threshold voltage and a method of manufacturing the same. A semiconductor device according to the present invention comprises a drift layer formed on a semiconductor substrate, first well regions formed in a surface layer of the drift layer, being apart from one another, a gate insulating film formed, extending on the drift layer and each of the first well regions, a gate electrode selectively formed on the gate insulating film, a source contact hole penetrating through the gate insulating film and reaching the inside of each of the first well regions, and a residual compressive stress layer formed on at least a side surface of the source contact hole, in which a compressive stress remains.

A method is provided in order to manufacture a silicon carbide epitaxial wafer whose surface flatness is very good and has a very low density of carrot defects and triangular defects arising after epitaxial growth. The silicon carbide epitaxial wafer is manufactured by a first step of annealing a silicon carbide bulk substrate that is tilted less than 5 degrees from &#x3c;0001&#x3e; face, in a reducing gas atmosphere at a first temperature Tfor a treatment time t, a second step of reducing the temperature of the substrate in the reducing gas atmosphere, and a third step of performing epitaxial growth at a second temperature Tbelow the annealing temperature Tin the first step, while supplying at least a gas including silicon atoms and a gas including carbon atoms.

Method of manufacturing silicon carbide epitaxial wafer

A film of an epitaxial layer that allows the reduction in both the height of a bunching step and crystal defects caused by a failure in migration of reactive species on a terrace is formed on a SiC semiconductor substrate having an off angle of 5 degrees or less. A film of a first-layer epitaxial layer is formed on and in contact with a surface of the SiC semiconductor substrate having an off angle of 5 degrees or less. Subsequently, the temperature in a reactor is lowered. A second-layer epitaxial layer is caused to epitaxially grow on and in contact with a surface of the first-layer epitaxial layer. In the above-described manner, the epitaxial layer is structured with two layers, and the growth temperature for the second epitaxial layer is set lower than the growth temperature for the first epitaxial layer.

Method for manufacturing silicon carbide semiconductor device

A magnetic storage device which enables stable operation at the time of recording information into MRAM and the stable retention of recorded information. The die of the magnetic storage device has a substrate, first and second wirings, a magnetic storage element and a first magnetic shielding structure. The first magnetic shielding structure is formed to cover the magnetic storage element in a plan view. Second and third magnetic shielding structures sandwich the die in a thickness direction. A lead frame member has the die mounted thereon and contains a ferromagnetic material. The lead frame member overlaps with only part of the die in a plan view.

Magnetic storage device

A semiconductor device excellent in the magnetic shielding effect of blocking off external magnetic fields is provided. The semiconductor device includes: an interlayer insulating film so formed as to cover a switching element formed over a main surface of a semiconductor substrate; a flat plate-like lead wiring; a coupling wiring coupling the lead wiring and the switching element with each other; and a magnetoresistive element including a magnetization free layer the orientation of magnetization of which is variable and formed over the lead wiring. The semiconductor device has a wiring and another wiring through which the magnetization state of the magnetization free layer can be varied. In a memory cell area where multiple magnetoresistive elements are arranged, a first high permeability film arranged above the magnetoresistive elements is extended from the memory cell area up to a peripheral area that is an area other than the memory cell area.

Semiconductor device and semiconductor device assembly

Growing community of inventors

Tokyo, Japan

Masayoshi Tarutani