International Business Machines Corporation

Masayoshi Taniguchi

Takashi Yanagisawa

Masayoshi Nakano

Jun Usami

Isamu Mashima

A method and apparatus to configure redundant memory elements in a system on a chip (SoC) having discrete voltage domains (islands). A plurality of memories are provided for each voltage island, each containing redundancy elements or having the capability to access redundant memory elements in a neighboring voltage domain; a fuse cell stores configuration information for controlling the switching of memory elements of the plurality of memories; a shift register receives and retains configuration information on a memory array from the fuse cell corresponding to each memory; and a control circuit directs operation of the shift register. The shift register includes a shift portion for receiving the data of the configuration information and transferring the data to another shift register, and a latch portion for retaining the data inputted to the shift portion. The control circuit controls whether or not the data of the shift register, which is inputted to the shift portion, is to be retained in the latch portion.

Method and apparatus for redundant memory configuration in voltage island

A microcomputer, a method for protecting memory and a method for performing debugging is provided including a TAP controller and instruction decoder for monitoring an external input for a processor, internal registers and comparators for determining whether or not the destination address of an access by the processor to ROM and SRAM is within a predetermined protected area, and internal registers and multiplexers as access control means. If a control instruction for the processor has been detected and an execution of an access from the processor to the protected area has been detected, the destination address of the access is replaced with addresses of a ROM and SRAM of an additional circuitry block that have been prepared by developers.

Microcomputer, a method for protecting memory and a method for performing debugging

A computer system has a central processing unit (&ldquo;CPU&rdquo;) and a plurality of peripheral devices. A bus interconnects the CPU and the peripheral devices. Command signals are transmitted over the bus including an initiator ready signal (&ldquo;IRDY&rdquo;), a device select signal (&ldquo;DEVSEL&rdquo;) and a target ready signal (&ldquo;TRDY&rdquo;). First and second direct memory access devices (&ldquo;DMA&rdquo;) are connected to the bus and assigned the same address space. First and second switches selectively connect and disconnect the DEVSEL and TRDY signals that are output from the first and second DMA devices, respectively. Controller logic receives the DEVSEL and TRDY signals and directs the opening and closing of the first and second switches.

Computer system having two DMA circuits assigned to the same address space

A computer system has a central processing unit ('CPU') and a plurality of peripheral devices. A bus interconnects the CPU and the peripheral devices. Command signals are transmitted over the bus including an initiator ready signal ('IRDY'), a device select signal ('DEVSEL'), and a target ready signal ('TRDY'). First and second direct memory access devices ('DMA') are connected to the bus and assigned the same address space. First and second switches selectively connect and disconnect the DEVSEL and TRDY signals that are output from the first and second DMA devices, respectively. Controller logic receives the DEVSEL and TRDY signals and directs the opening and closing of the first and second switches.

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Shiga-ken, Japan

Masayoshi Taniguchi