Fujitsu Corporation

Nippon Telegraph and Telephone Corporation

Masayoshi Sekido

Hiroyuki Sato

Junichi Tamura

Kazuyuki Tajima

Haruo Yamashita

Masaaki Kawai

Jinichi Yoshizawa

Yuji Takizawa

Hidetoshi Naito

Hideo Tatsuno

Hiroomi Tateishi

Satomi Ikeda

A 1-bit error correction circuit based on CRC calculation is provided with a syndrome generation circuit which determines input parallel data of m bits and which have been converted from n number of m-bit serial data. A 1-bit error detection circuit cyclically supplies a syndrome to a remainder calculation circuit and decodes remainder data obtained from this cyclic supply and detects 1-bit errors. A actual data reproduction circuit calculates the exclusive OR of output data of a predetermined register of a 1'st.about.n'th register of a syndrome generation circuit and data supplied to a predetermined register and obtains parallel data which is the actual data. A correction circuit which calculates a exclusive OR of parallel data obtained from a actual data reproduction circuit and 1-bit error data detected by the 1-bit error detection circuit and outputs corrected data.

One bit error correction method having actual data reproduction function

A write address counter for designating a write address of a memory counts up a control counter with an address change. A read address counter for designating a read address of the memory counts down the control counter with the address change. Inputted to an error detecting circuit are a write address counter value, a read address counter value and a control count value. There is detected whether a relationship such as Write Address Count Value-Read Address Count Value=Control Count Value is established or not. If not established, this implies an error, and a reset circuit resets each counter.

Apparatus for and a method of detecting a malfunction of a FIFO memory

Growing community of inventors

Kawasaki, Japan

Masayoshi Sekido